Operating method for a memory, a memory and a memory system

Patent metadata

Field	Value
Publication number	US-2025046383-A1
Application number	US-202418927349-A
Country	US
Kind code	A1
Filing date	Oct 25, 2024
Priority date	Oct 20, 2022
Publication date	Feb 6, 2025
Grant date	—

Abstract

A memory device includes. a memory controller configured to send a first command, and a memory coupled to the memory controller. The memory is configured to in response to the first command, perform first read operations based on a first set of read voltages. The first set of read voltages includes first read voltages. Any two adjacent first read voltages have an equal offset with a first value. Each first read operation is performed based on one first read voltage. The memory is also configured to obtain first quantities of memory cells meeting set conditions, each of which corresponds to a read result of one first read operation. The memory is further configured to send first information corresponding to the first quantities of memory cells meeting the set conditions to the memory controller. The memory controller is further configured to obtain first differences each between two first quantities corresponding to two adjacent first read voltages with the first information received from the memory, determine an optimal read voltage based on the first differences, and send one or more second commands to the memory indicating the memory to perform read operations based on the optimal read voltage.

First claim

1 . A memory system, comprising:
a memory controller configured to send a first command; and a memory coupled to the memory controller and configured to:
in response to the first command, perform first read operations based on a first set of read voltages, the first set of read voltages comprising a plurality of first read voltages, any two adjacent first read voltages of the plurality of first read voltages having an equal offset with a first value, and each first read operation being performed based on one first read voltage of the plurality of first read voltages;
obtain first quantities of memory cells meeting set conditions, each first quantity of memory cells corresponding to a read result of one first read operation; and
send first information corresponding to the first quantities of memory cells meeting the set conditions to the memory controller;
wherein the memory controller is further configured to:
obtain first differences each between two first quantities corresponding to two adjacent first read voltages with the first information received from the memory;
determine an optimal read voltage based on the first differences; and
send one or more second commands to the memory, the one or more second commands indicating the memory to perform read operations based on the optimal read voltage.

2 . The memory system of claim 1 , wherein the plurality of first read voltages comprise a first voltage and at least two second voltages, and each of the at least two second voltages is an offset voltage value with a certain offset relative to the first voltage.

3 . The memory system of claim 1 , wherein the memory comprises a memory array having memory cells and a peripheral circuit coupled to the memory array, and the first quantities of memory cells are obtained by the peripheral circuit.

4 . The memory system of claim 3 , wherein the memory array comprising a memory plane, and the peripheral circuit is configured to:
perform the first read operations in the memory plane based on the plurality of first read voltages; and obtain the first quantities of memory cells meeting the set conditions.

5 . The memory system of claim 1 ,
wherein the first information comprises the first differences obtained by the memory; and the memory is configured to send the first differences to the memory controller; or wherein the first information comprises the first quantities of memory cells meeting the set conditions; and the memory controller is further configured to obtain the first differences with the first quantities of memory cells.

6 . The memory system of claim 1 , wherein the determining of the optimal read voltage comprises:
obtaining a relationship between a first change trend of the first differences and a second change trend of the plurality of first read voltages; and determining the optimal read voltage based on the relationship.

7 . The memory system of claim 6 , wherein the plurality of first read voltages comprise a first voltage and at least two second voltages, and in response to the first change trend of the first differences being consistent with the second change trend of the plurality of first read voltages, the determining of the optimal read voltage based on the relationship comprises:
obtaining a first offset direction of the optimal read voltage with respect to the first voltage based on the relationship; obtaining a first optimal offset based on the first offset direction; and determining the optimal read voltage based on the first optimal offset and the first voltage.

8 . The memory system of claim 7 , wherein:
in response to the at least two second voltages being sequentially decreasing with respect to the first voltage, the first offset direction of the optimal read voltage with respect to the first voltage is leftward; and in response to the at least two second voltages being sequentially increasing with respect to the first voltage, the first offset direction of the optimal read voltage with respect to the first voltage is rightward.

9 . The memory system of claim 6 , wherein the plurality of first read voltages comprise a first voltage and at least two second voltages, and in response to the first change trend of the first differences being inconsistent with the second change trend of the plurality of first read voltages, the determining of the optimal read voltage based on the relationship comprises:
obtaining a minimum one of the first differences; obtaining two first read voltages corresponding to the minimum one of the first differences from the first voltage and the at least two second voltages; and determining a voltage value between the two first read voltages to be the optimal read voltage.

10 . The memory system of claim 1 , wherein the memory is further configured to:
in response to the first command, perform second read operations based on a second set of read voltages, wherein:
the second set of read voltages comprises a plurality of second read voltages;
any two adjacent second read voltages of the plurality of second read voltages have an equal offset with a second value; and
each second read operation is performed based on one second read voltage of the plurality of second read voltages;
obtain second quantities of memory cells meeting the set conditions, each second quantity of memory cells corresponding to a read result of one second read operation; and send second information corresponding to the second quantities of memory cells meeting the set conditions to the memory controller;
the memory controller is further configured to:
obtain second differences each between two second quantities corresponding to two adjacent second read voltages with the second information received from the memory; and
determine the optimal read voltage based on at least one of the first differences or the second differences.

11 . The memory system of claim 10 , wherein the plurality of first read voltages comprise a first voltage and at least two second voltages, and the plurality of second read voltages comprise a third voltage and at least two fourth voltages; and
wherein the determining of the optimal read voltage based on at least one of the first differences or the second differences comprises: in response to a first change trend of the first differences being inconsistent with a second change trend of the plurality of first read voltages, and a third change trend of the second differences being consistent with a fourth change trend of the plurality of second read voltages, determining the optimal read voltage based on a minimum one of the first differences; in response to the first change trend of the first differences being consistent with the second change trend of the plurality of first read voltages, and the third change trend of the second differences being inconsistent with the fourth change trend of the plurality of second read voltages, determining the optimal read voltage based on a minimum one of the second differences; in response to the first change trend of the first differences being inconsistent with the second change trend of the plurality of first read voltages, and the third change trend of the second differences being inconsistent with the fourth change trend of the plurality of second read voltages, determining the optimal read voltage based on at least one of the minimum one of the first differences or the minimum one of the second differences; and in response to the first change trend of the first differences being consistent with the second change trend of the plurality of first read voltages, and the third change trend of the second differences being consistent with the fourth change trend of th

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Cheng Boxuan
• Guo Lu

Classifications

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/30

  Power supply circuits · CPC title

• G11C16/28 Primary

  using differential sensing or reference cells, e.g. dummy cells · CPC title

• G11C11/5642

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/26 Primary

  Sensing or reading circuits; Data output circuits · CPC title