Method for driving display scaler in video mode and electronic device using same method

US2025046269A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2025046269-A1
Application numberUS-202418921657-A
CountryUS
Kind codeA1
Filing dateOct 21, 2024
Priority dateApr 28, 2022
Publication dateFeb 6, 2025
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An electronic device is provided. The electronic device includes a display, a display driver IC (DDI) configured to drive the display on the basis of a video mode, memory storing one or more computer programs, and one or more processors communicatively coupled to the display, the DDI, and the memory, wherein the one or more computer programs include computer-executable instructions that, when executed by the one or more processors individually or collectively, cause the electronic device to generate first image data corresponding to a first resolution, generate second image data by adding a blank section to at least some sections of the first image data, and transmit the second image data to the DDI, and wherein the DDI comprises an upscaler configured to convert the second image data input from the one or more processors into third image data corresponding to a second resolution larger than the first resolution by a designated ratio, and is configured to drive the display so that the display displays the third image data.

First claim

Opening claim text (preview).

What is claimed is: 1 . An electronic device, comprising: a display; a display driver IC (DDI) configured to drive the display based on a video mode; memory storing one or more computer programs; and one or more processors communicatively coupled to the display, the DDI, and the memory, wherein the one or more computer programs include computer-executable instructions that, when executed by the one or more processors individually or collectively, cause the electronic device to: generate first image data corresponding to a first resolution, generate second image data by adding a blank section to at least some sections of the first image data, and transmit the second image data to the DDI, and wherein the DDI comprises an upscaler configured to convert the second image data input from the one or more processors into third image data corresponding to a second resolution larger than the first resolution by a designated ratio, and is configured to drive the display so that the display displays the third image data. 2 . The electronic device of claim 1 , wherein the DDI does not comprise a buffer memory configured to store the second image data input from the one or more processors. 3 . The electronic device of claim 1 , wherein the one or more processors comprises: an image generator configured to generate the first image data based on an executed application; a buffer memory configured to store the first image data; and a timing controller configured to generate the second image data by adjusting output timing of the first image data according to the designated ratio. 4 . The electronic device of claim 3 , wherein the timing controller is configured to: change a first horizontal synchronization signal corresponding to the first resolution to a second horizontal synchronization signal corresponding to the second resolution based on the designated ratio; adjust a length of each transmission section of the first image data based on the second horizontal synchronization signal; and convert the first image data into the second image data by adding the blank section between at least some sections of the adjusted transmission sections of the first image data. 5 . The electronic device of claim 4 , wherein, when converting the first image data into the second image data, the timing controller is configured to divide transmission sections of the first image data into a plurality of unit sections in which horizontal line data of the first image data are arranged according to a designated rule, and each of the plurality of unit sections comprises at least one blank section between the horizontal line data of the first image data. 6 . The electronic device of claim 5 , wherein each of the plurality of unit sections has a total length of the K1 number of horizontal periods based on the designated magnification, and includes K2 number of horizontal line data and (K1-K2) number of blank sections, and wherein the designated magnification is K1/K2. 7 . The electronic device of claim 6 , wherein the upscaler is configured to generate the K1 number of horizontal line data using the K2 number of horizontal line data included in each of the plurality of unit sections, when converting the second image data into the third image data. 8 . The electronic device of claim 3 , wherein the timing controller comprises an encoder configured to encode the first image data generated by the image generator based on a designated standard; and wherein the encoder is configured to provide the encoded first image data to the timing controller. 9 . The electronic device of claim 8 , wherein the DDI comprises a decoder configured to receive an input of the second image data encoded according to the designated standard from the one or more processors; and wherein the decoder is configured to decode the input second image data according to the designated standard and to provide the decoded second image data to the upscaler. 10 . The electronic device of claim 8 , wherein the timing controller is configured to continuously transmit the designated K number of horizontal line data transmitted first among the N number of horizontal line data included in first image data encoded by the encoder without a blank section. 11 . A method performed by an electronic device including a display driver IC (DDI) configured to drive a display based on a video mode, the method comprising: generating, by one or more processors, first image data corresponding to a first resolution; generating, by the one or more processors, second image data by adding a blank section to at least some sections of the first image data; transmitting, by the one or more processors, the second image data to the DDI; converting, by an upscaler of the DDI, the second image data input from the one or more processors into third image data corresponding to a second resolution larger than the first resolution by a designated ratio; and driving, by the DDI, the display so that the display displays the third image data. 12 . The method of claim 11 , wherein the DDI does not comprise a buffer memory configured to store the second image data input from the one or more processors. 13 . The method of claim 11 , wherein the one or more processors comprises: an image generator configured to generate the first image data based on an executed application; a buffer memory configured to store the first image data; and a timing controller configured to generate the second image data by adjusting output timing of the first image data according to the designated ratio. 14 . The method of claim 13 , further comprising: changing, by the timing controller, a first horizontal synchronization signal corresponding to the first resolution to a second horizontal synchronization signal corresponding to the second resolution based on the designated ratio; adjusting, by the timing controller, a length of each transmission section of the first image data based on the second horizontal synchronization signal; and converting, by the timing controller, the first image data into the second image data by adding the blank section between at least some sections of the adjusted transmission sections of the first image data. 15 . The method of claim 14 , further comprising: dividing, by the timing controller, transmission sections of the first image data into a plurality of unit sections in which horizontal line data of the first image data are arranged according to a designated rule, wherein each of the plurality of unit sections comprises at least one blank section between the horizontal line data of the first image data. 16 . The method of claim 15 , wherein each of the plurality of unit sections has a total length of the K1 number of horizontal periods based on the designated magnification, and includes K2 number of horizontal line data and (K1-K2) number of blank sections, and wherein the designated magnification is K1/K2. 17 . The method of claim 16 , wherein the upscaler is configured to generate the K1 number of horizontal line data using the K2 number of horizontal line data included in each of the plurality of unit sections, when converting the second image data into the third image data. 18 . The method of claim 13 , wherein the timing controller comprises an encoder configured to encode the first image data generated by the image generator based on a designated standard; and wherein the encoder is configured to provide the encoded first image data to the timing controller.

Assignees

Inventors

Classifications

  • Horizontal resolution change · CPC title

  • Graphics controller able to handle multiple formats, e.g. input or output formats · CPC title

  • Details of the interface to the display terminal (specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04) · CPC title

  • Timing circuits for raster scan displays (specially adapted for television H04N {; synchronisation between the display unit and other display units, videodisc player G09G5/12}) · CPC title

  • for resetting or blanking · CPC title

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What does patent US2025046269A1 cover?
An electronic device is provided. The electronic device includes a display, a display driver IC (DDI) configured to drive the display on the basis of a video mode, memory storing one or more computer programs, and one or more processors communicatively coupled to the display, the DDI, and the memory, wherein the one or more computer programs include computer-executable instructions that, when e…
Who is the assignee on this patent?
Samsung Electronics Co Ltd
What technology area does this patent fall under?
Primary CPC classification G09G5/227. Mapped technology areas include Physics.
When was this patent published?
Publication date Thu Feb 06 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).