Systems and methods for policy execution processing

Patent metadata

Field	Value
Publication number	US-2025045056-A1
Application number	US-202418924611-A
Country	US
Kind code	A1
Filing date	Oct 23, 2024
Priority date	Feb 2, 2018
Publication date	Feb 6, 2025
Grant date	—

Abstract

A system and method of processing instructions may comprise an application processing domain (APD) and a metadata processing domain (MTD). The APD may comprise an application processor executing instructions and providing related information to the MTD. The MTD may comprise a tag processing unit (TPU) having a cache of policy-based rules enforced by the MTD. The TPU may determine, based on policies being enforced and metadata tags and operands associated with the instructions, that the instructions are allowed to execute (i.e., are valid). The TPU may write, if the instructions are valid, the metadata tags to a queue. The queue may (i) receive operation output information from the application processing domain, (ii) receive, from the TPU, the metadata tags, (iii) output, responsive to receiving the metadata tags, resulting information indicative of the operation output information and the metadata tags; and (iv) permit the resulting information to be written to memory.

First claim

What is claimed is:

1 . A method of processing instructions, comprising:
(a) in an application processing domain, by an application processor:
implementing a first instruction set architecture;
receiving instructions comprising operand information indicative of one or more operands, and operation information indicative of an operation to be performed on the one or more operands, the instructions being formatted in accordance with the first instruction set architecture; and
providing, to a metadata processing domain, the instructions in an instruction stream; and
(b) in the metadata processing domain:
by a tag processing unit comprising at least one decode table:
extract the operand information and the operation information from the instructions.

2 . The method of claim 1 , wherein the tag processing unit comprises at least one look-up table configured to determine, based on the instructions, instruction care bit information indicative of one or more care bits, and operation group information indicative of an operation group.

3 . The method of claim 1 , further comprising determining, by the tag processing unit based on the at least one decode table, that the instructions are formatted in accordance with the first instruction set architecture.

4 . The method of claim 3 , wherein a determination that the instructions are formatted in accordance with the first instruction set architecture is further based on the instruction care bit information indicative of the one or more care bits and the operation group information indicative of an operation group.

5 . The method of claim 3 , wherein the at least one decode table comprises a cascade of tables of at least a primary table, a secondary table, and a plurality of address lookup tables.

6 . The method of claim 1 , wherein the tag processing unit further comprises a buffered interface configured to store the instructions from the application processor when the tag processing unit is stalled, and to provide stored instructions for use by the tag processing unit when the instruction stream is stalled.

7 . The method of claim 1 , wherein the buffered interface comprises a first-in-first-out (FIFO) component.

8 . The method of claim 1 , wherein the tag processing unit further comprises a tag map table (TMT) configured to convert one or both of a physical instruction address and a data memory page address, into one or both of (i) a corresponding associated tag addresses and (ii) directly into a tag.

9 . The method of claim 8 , wherein the TMT is configured to accommodate an immediate value tag, specified for a particular size of a memory region, the particular size being selected from a range of memory region sizes.

10 . The method of claim 1 , wherein the metadata processing domain further comprises a Metadata Tag Interlock Queue, and further comprising by the Metadata Tag Interlock Queue:
(i) performing a first write to change a tag address to a predetermined constant value that indicates a write transaction is underway; (ii) performing a second write to write new data; and (iii) performing a third write to write a new tag associated with the new data.

Assignees

• Charles Stark Draper Laboratory Inc

Inventors

• Milburn Steve E
• Boling Eli
• Dehon Andre'
• Sutherland Andrew B
• Sullivan Gregory T

Classifications

• G06F21/575

  Secure boot · CPC title

• G06F12/1009

  using page tables, e.g. page table structures · CPC title

• G06F9/30145 Primary

  Instruction analysis, e.g. decoding, instruction word fields · CPC title

• G06F16/24

  Querying · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title