Memory device and method

Patent metadata

Field	Value
Publication number	US-2025044990-A1
Application number	US-202418922285-A
Country	US
Kind code	A1
Filing date	Oct 21, 2024
Priority date	Mar 20, 2019
Publication date	Feb 6, 2025
Grant date	—

Abstract

A memory device includes a data latch, a nonvolatile memory cell array, and a control circuit configured to: manage information about an operation period of a sense operation, the sense operation being an operation in which the control circuit reads data stored in the nonvolatile memory cell array into the data latch, and in response to an inquiry instruction from a memory controller, output, to the memory controller, the information about the operation period of the sense operation.

First claim

What is claimed is:

1 . A memory device comprising:
a data latch; a nonvolatile memory cell array; and a control circuit configured to:
manage information about an operation period of a sense operation, the sense operation being an operation in which the control circuit reads data stored in the nonvolatile memory cell array into the data latch; and
in response to an inquiry instruction from a memory controller, output, to the memory controller, the information about the operation period of the sense operation.

2 . The memory device according to claim 1 , wherein
the control circuit is configured to determine the information about the operation period of the sense operation based on a read condition received from the memory controller together with an inquiry about the information, and then output the information to the memory controller.

3 . The memory device according to claim 1 , wherein
the control circuit is configured to determine the information about the operation period of the sense operation based on a read command issued by the memory controller, and then output the information in response to an inquiry about the information from the memory controller.

4 . The memory device according to claim 1 , further comprising:
a storage circuit that stores the information about the operation period of the sense operation, wherein the information about the operation period of the sense operation is stored in the storage circuit at time of manufacturing of the memory device.

5 . The memory device according to claim 4 , wherein
the storage circuit is different from the nonvolatile memory cell array.

6 . The memory device according to claim 4 , wherein
the storage circuit stores a plurality of pieces of information about the operation period of the sense operation, and the control circuit is configured to select, on the basis of a read condition of the sense operation designated by the memory controller, one of the plurality of pieces of information to output to the memory controller.

7 . The memory device according to claim 6 , wherein
the read condition includes at least one of(A) a type of read method,(B) a type of storage method, and (C) a page type.

8 . The memory device according to claim 1 , wherein the control circuit is configured to:
receive a sense instruction from the memory controller, the sense instruction being an instruction to cause the control circuit to execute the sense operation; and output, to the memory controller, a start time of the sense operation.

9 . The memory device according to claim 1 , wherein the control circuit is configured to:
receive a sense instruction from the memory controller, the sense instruction being an instruction to cause the control circuit to execute the sense operation; and output, to the memory controller, a scheduled end time of the sense operation.

10 . The memory device according to claim 1 , wherein
the control circuit is further configured to indicate, to the memory controller, a busy state of the memory device for a time period of the operation period of the sense operation.

11 . A method of controlling a memory device, the memory device including a data latch and a nonvolatile memory cell array, said method comprising:
managing information about an operation period of a sense operation, the sense operation being an operation in which data stored in the nonvolatile memory cell array is read into the data latch; and in response to an inquiry instruction from a memory controller, outputting, to the memory controller, the information about the operation period of the sense operation.

12 . The method according to claim 11 , further comprising:
determining the information about the operation period of the sense operation based on a read condition received from the memory controller together with an inquiry about the information, and then outputting the information to the memory controller.

13 . The method according to claim 11 , further comprising:
determining the information about the operation period of the sense operation based on a read command issued by the memory controller, and then outputting the information in response to an inquiry about the information from the memory controller.

14 . The method according to claim 11 , wherein
the memory device further includes a storage circuit that stores the information about the operation period of the sense operation, and the information about the operation period of the sense operation is stored in the storage circuit at time of manufacturing of the memory device.

15 . The method according to claim 14 , wherein
the storage circuit is different from the nonvolatile memory cell array.

16 . The method according to claim 14 , wherein:
the storage circuit stores a plurality of pieces of information about the operation period of the sense operation, and the method further comprises:
selecting, on the basis of a read condition of the sense operation designated by the memory controller, one of the plurality of pieces of information to output to the memory controller.

17 . The method according to claim 16 , wherein
the read condition includes at least one of (A) a type of read method, (B) a type of storage method, and (C) a page type.

18 . The method according to claim 11 , further comprising:
receiving a sense instruction from the memory controller, the sense instruction being an instruction to execute the sense operation; and outputting, to the memory controller, a start time of the sense operation.

19 . The method according to claim 11 , further comprising:
receiving a sense instruction from the memory controller, the sense instruction being an instruction to execute the sense operation; and outputting, to the memory controller, a scheduled end time of the sense operation.

20 . The method according to claim 11 , further comprising:
indicating, to the memory controller, a busy state of the memory device for a time period of the operation period of the sense operation.

Assignees

• Kioxia Corp

Inventors

• Sia Marie
• Kojima Yoshihisa
• Nishikawa Suguru
• Suzuki Riki

Classifications

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G11C11/5642

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C11/5671

  using charge trapping in an insulator · CPC title