Method for manufacturing thin film transistor, and electronic device

Patent metadata

Field	Value
Publication number	US-2025040192-A1
Application number	US-202418918548-A
Country	US
Kind code	A1
Filing date	Oct 17, 2024
Priority date	May 31, 2017
Publication date	Jan 30, 2025
Grant date	—

Abstract

Disclosed are a thin film transistor (TFT) including an oxide semiconductor layer capable of being applied to high-resolution flat panel display devices requiring high-speed driving, a gate driver including the TFT, and a display device including the gate driver. The TFT includes first oxide semiconductor layer consisting of indium-gallium-zinc-tin oxide (IGZTO) and a second oxide semiconductor layer including indium-gallium-zinc oxide (IGZO). A content ratio (Ga/In) of gallium (Ga) to indium (In) of the second oxide semiconductor layer is higher than a content (Ga/In) of Ga to In of the first oxide semiconductor layer, and a content ratio (Zn/In) of zinc (Zn) to In of the second oxide semiconductor layer is higher than a content (Zn/In) of Zn to In of the first oxide semiconductor layer.

First claim

1 . A thin film transistor comprising:
a first oxide semiconductor layer including indium (In), gallium (Ga), zinc (Zn), tin (Sn) and oxygen (O); a second oxide semiconductor layer including indium (In), gallium (Ga), zinc (Zn) and oxygen (O), wherein the second oxide semiconductor layer is disposed on the first oxide semiconductor layer; and a gate electrode disposed closer to the first oxide semiconductor layer than the second oxide semiconductor layer, wherein
a content ratio (Ga/In) of Ga to In of the second oxide semiconductor layer is higher than a content ratio (Ga/In) of Ga to In of the first oxide semiconductor layer, and
a content ratio (Zn/In) of Zn to In of the second oxide semiconductor layer is equal to or higher than a content ratio (Zn/In) of Zn to In of the first oxide semiconductor layer,
wherein
an inclined angle of one side surface of the first oxide semiconductor layer is an acute angle, and
an inclined angle of one side surface of the second oxide semiconductor layer is 90 degrees or an acute angle.

2 . The thin film transistor of claim 1 , wherein a content ratio (Zn/In) of Zn to In of the second oxide semiconductor layer is lower than 5.

3 . The thin film transistor of claim 1 , wherein a thickness of the second oxide semiconductor layer is thicker than one-third of a thickness of the first oxide semiconductor layer and thinner than five-third of the thickness of the first oxide semiconductor layer.

4 . The thin film transistor of claim 1 , wherein the gate electrode is disposed under the first oxide semiconductor layer.

5 . The thin film transistor of claim 4 , further comprising:
a source electrode contacting one side of the first oxide semiconductor layer and one side of the second oxide semiconductor layer; and a drain electrode contacting another side of the first oxide semiconductor layer and another side of the second oxide semiconductor layer.

6 . The thin film transistor of claim 5 , wherein a length of the first oxide semiconductor layer in a direction in which the source electrode and the drain electrode are separated from each other is longer than a length of the second oxide semiconductor layer in the direction in which the source electrode and the drain electrode are separated from each other.

7 . A gate driver comprising a plurality of stages outputting gate signals, the plurality of stages each including a thin film transistor,
wherein the thin film transistor comprising: a first oxide semiconductor layer including indium (In), gallium (Ga), zinc (Zn), tin (Sn) and oxygen (O); and a second oxide semiconductor layer including indium (In), gallium (Ga), zinc (Zn) and oxygen (O), wherein
a content ratio (Ga/In) of Ga to In of the second oxide semiconductor layer is higher than a content ratio (Ga/In) of Ga to In of the first oxide semiconductor layer, and
a content ratio (Zn/In) of Zn to In of the second oxide semiconductor layer is equal to or higher than a content ratio (Zn/In) of Zn to In of the first oxide semiconductor layer.

8 . A display device comprising a display panel including a plurality of data lines, a plurality of gate lines, and a plurality of pixels respectively provided in a plurality of areas defined by intersections of the plurality of data lines and the plurality of gate lines, the plurality of pixels each including a thin film transistor,
wherein the thin film transistor comprising:
a first oxide semiconductor layer including indium (In), gallium (Ga), zinc (Zn), tin (Sn) and oxygen (O); and
a second oxide semiconductor layer including indium (In), gallium (Ga), zinc (Zn) and oxygen (O),
wherein
a content ratio (Ga/In) of Ga to In of the second oxide semiconductor layer is higher than a content ratio (Ga/In) of Ga to In of the first oxide semiconductor layer, and
a content ratio (Zn/In) of Zn to In of the second oxide semiconductor layer is equal to or higher than a content ratio (Zn/In) of Zn to In of the first oxide semiconductor layer.

9 . The display device of claim 8 , wherein
the display panel further comprises a gate driver outputting gate signals to the plurality of gate lines, and the gate driver comprises the thin film transistor.

10 . A method of manufacturing a thin film transistor comprising:
forming a gate electrode on a substrate; depositing a gate dielectric layer on the gate electrode; forming a first oxide semiconductor layer including indium (In), gallium (Ga), zinc (Zn), tin (Sn), and oxygen (O); and forming a second oxide semiconductor layer including indium (In), gallium (Ga), zinc (Zn), and oxygen (O), wherein a content ratio Ga/Zn of the second oxide semiconductor layer is higher than a content ratio Ga/Zn of the first oxide semiconductor layer, wherein in the first oxide semiconductor layer, a content ratio of In to Sn satisfies 2.5≤In/Sn≤5, a content ratio of Ga to Sn satisfies 1≤Ga/Sn≤2, and a content ratio of Zn to Sn satisfies 2.5≤Zn/Sn≤5, and wherein the content ratio of Ga/Zn of the first oxide semiconductor layer is less than 1 and the content ratio of Ga/Zn of the second oxide semiconductor layer is 1 or more.

11 . The method of claim 10 , further comprising:
forming the second oxide semiconductor layer overlying the first oxide semiconductor layer while the substrate is within a first selected temperature range during the formation of the first oxide semiconductor layer, and the substrate is within a second selected temperature range different from the first selected temperature range during the formation of the second oxide semiconductor layer.

12 . The method of claim 11 , wherein both the first and second selected temperature ranges each have a bottom value equal to or higher than 200° C.

13 . The method of claim 11 , wherein the first selected temperature range has a bottom value that is higher than a bottom value of the second selected temperature range.

14 . The method of claim 1 , further comprising:
etching the second oxide semiconductor layer; and etching the first oxide semiconductor layer.

15 . The method of claim 14 , wherein the first and second oxide semiconductor layers are etched sequentially.

16 . The method of claim 14 , wherein an etch rate of the first oxide semiconductor layer is substantially equal to or lower than that of the second oxide semiconductor layer.

17 . The method of claim 14 , wherein a slope of each of side surfaces of the first oxide semiconductor layer is formed at an acute angle and a slope of each of side surfaces of the second oxide semiconductor layer is formed at an acute angle or a right angle.

18 . The method of claim 10 , further comprising:
forming a source electrode and a drain electrode on the second oxide semiconductor layer and the gate dielectric layer.

19 . The method of claim 18 , wherein each of the source electrode and the drain electrode contacts the first and second oxide semiconductor layers and the gate dielectric layer.

20 . The method of claim 10 , wherein a content ratio (Zn/In) of Zn to In of the second oxide semiconductor layer is lower than 5.

Assignees

• Lg Display Co Ltd

Inventors

• Kim Seungjin
• Lee Heesung
• Lee Sohyung
• Kim Mincheol
• YANG Jeongsuk
• Park Jeeho
• Im Seoyeon

Classifications

• H10P14/3426

  Oxides · CPC title

• H10D99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10D86/423

  comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D62/80

  characterised by the materials · CPC title