Semiconductor memory device and method of operating the semiconductor memory device

Patent metadata

Field	Value
Publication number	US-2025037778-A1
Application number	US-202418913146-A
Country	US
Kind code	A1
Filing date	Oct 11, 2024
Priority date	May 26, 2021
Publication date	Jan 30, 2025
Grant date	—

Abstract

A method of operating a semiconductor memory device includes a plurality of program loops for programming selected memory cells among a plurality of memory cells. Each of the plurality of program loops includes setting a state of a bit line connected to the selected memory cells, applying a program voltage to a word line connected to the selected memory cells, and performing a verify operation on the selected memory cells using a first pre-verify voltage, a second pre-verify voltage greater than the first pre-verify voltage, and a main verify voltage greater than the second pre-verify voltage. A first program permission cell, a second program permission cell, a third program permission cell, and a program prohibition cell are determined by performing the verify operation.

First claim

What is claimed is:

1 . A method of operating a semiconductor memory device including a plurality of program loops for programming selected memory cells among a plurality of memory cells to a first program state higher than an erase state and a second program state higher than the first program state, wherein each of the plurality of program loops comprises:
applying a program voltage to a word line connected to the selected memory cells; applying a verify voltage to a selected word line connected to the selected memory cells; comparing bit line currents corresponding to the selected memory cells and different reference currents; applying, based on a result of the comparing, a first program permission voltage, a second program permission voltage greater than the first program permission voltage, a third program permission voltage greater than the second program permission voltage, or a program prohibition voltage greater than the third program permission voltage to bit lines connected to first memory cells to be programmed to the first program state among the selected memory cells; and applying the first program permission voltage to bit lines connected to second memory cells to be programmed to the second program state among the selected memory cells when the first memory cells are programed.

2 . The method of claim 1 , wherein the different reference currents include a first reference current, a second reference current less than the first reference current, and a third reference current less than the second reference current.

3 . The method of claim 2 , wherein the first reference current is compared to the bit line currents, then the second reference current is compared to the bit line currents, and then the third reference current is compared to the bit line currents.

4 . The method of claim 1 , wherein the verify voltage is applied to the selected word line during the comparing of the bit line currents and the different reference currents.

5 . The method of claim 2 , wherein when the bit line currents are compared to the different reference currents,
memory cells, among the first memory cells, which are connected to bit lines having a current greater than the first reference current are determined as first program permission cells, memory cells, among the first memory cells, which are connected to bit lines having a current between the first reference current and the second reference current are determined as second program permission cells, and memory cells, among the first memory cells, which are connected to bit lines having a current between the second reference current and the third reference current are determined as third program permission cells.

6 . The method of claim 5 , wherein the first program permission voltage is applied to the bit lines connected to the first program permission cells,
the second program permission voltage is applied to the bit lines connected to the second program permission cells, and the third program permission voltage is applied to the bit lines connected to the third program permission cells.

Assignees

• Sk Hynix Inc

Inventors

• Lee Hee Youl

Classifications

• G11C11/5628

  Programming or writing circuits; Data input circuits · CPC title

• G11C11/5671

  using charge trapping in an insulator · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title