Enhanced end to end protection in key value storage devices

Patent metadata

Field	Value
Publication number	US-2025036814-A1
Application number	US-202318359167-A
Country	US
Kind code	A1
Filing date	Jul 26, 2023
Priority date	Jul 26, 2023
Publication date	Jan 30, 2025
Grant date	—

Abstract

Key value (KV) pair data includes a key and a value, where the key addresses the value. The value may include one or more flash management units (FMUs). Because the value is read in order, sequentially from one FMU to a next FMU, end-to-end (E2E) protection of the value may be optimized and improved. E2E protection may including using checksum signatures, of which cyclic redundancy code (CRC) signatures are but one example, to ensure that corrupted data is not returned to a host device. Optimizing checksum signatures used to protect the value may include generating an aggregated checksum signature for each FMU based on a current FMU and each previous FMU of the value or only generating a single checksum signature for an entirety of the value. Thus, characteristics of the value may be taken advantage of in order to improve and optimize E2E protection.

First claim

What is claimed is:

1 . A data storage device, comprising:
a memory device; and a controller coupled to the memory device, wherein the controller is configured to:
receive key value (KV) pair data from a host device, wherein:
the KV pair data comprises a key and a value;
the key addresses the value; and
the value comprises two or more flash management units (FMUs);

generate a first checksum signature for the received value, wherein the first checksum signature is generated for an aggregated number of consecutive adjacent FMUs of the value; and
program the generated first checksum signature and the value to the memory device.

2 . The data storage device of claim 1 , wherein the aggregated number of consecutive adjacent FMUs of the value is all of the FMUs of the value.

3 . The data storage device of claim 1 , wherein the aggregated number of consecutive adjacent FMUs of the value for the first checksum signature is a first FMU of the value.

4 . The data storage device of claim 3 , wherein the controller is further configured to:
generate a second checksum signature for the received value, wherein:
the second checksum signature is generated for an aggregated number of consecutive adjacent FMUs of the value; and
the aggregated number of consecutive adjacent FMUs of the second checksum signature is the first FMU and a second FMU of the value.

5 . The data storage device of claim 4 , wherein the first checksum signature and the second checksum signature are a same size and wherein the first checksum is a cyclic redundancy code (CRC) signature.

6 . The data storage device of claim 4 , wherein the second checksum signature is a predetermined size larger than the first checksum signature.

7 . The data storage device of claim 1 , wherein the first checksum signature is for the two or more FMUs.

8 . The data storage device of claim 1 , wherein the first checksum signature is generated after a last FMU of the two or more FMUs is received from a host.

9 . The data storage device of claim 1 , wherein the controller is further configured to:
receive the key from a host device; utilize the key to retrieve the value from the memory device, wherein retrieving the value further comprises retrieving the first checksum signature; generate a read checksum signature for the value retrieved from the memory device; and determine whether the read checksum signature matches the first checksum signature.

10 . The data storage device of claim 9 , wherein the controller is further configured to:
send the value to the host device when the read checksum signature matches the first checksum signature.

11 . The data storage device of claim 9 , wherein the controller is further configured to:
send an error message to the host device when the read checksum signature does not match the first checksum signature.

12 . A data storage device, comprising:
a memory device; and a controller coupled to the memory device, wherein the controller is configured to:
generate a checksum signature for a value of a key value (KV) pair data, wherein:
the KV pair data comprises a key and the value;
the key addresses the value;
the value comprises a plurality of flash management units (FMUs); and
the checksum signature is generated for a first FMU and each two or more consecutive adjacent FMUs after the first FMU.

13 . The data storage device of claim 12 , wherein the checksum signature is programmed to the memory device with a last FMU of the plurality of FMUs of the value.

14 . The data storage device of claim 12 , wherein the controller is further configured to:
receive the key in a read request for the value, wherein the key further includes a specific FMU of the value; and retrieve the value and the checksum signature from the memory device, wherein the checksum signature retrieved corresponds with the specific FMU of the value.

15 . The data storage device of claim 12 , wherein the controller is further configured to:
receive the key in a read request for the value, wherein the key further includes a specific FMU of the value; and retrieve the value and the checksum signature from the memory device, wherein the checksum signature retrieved corresponds with the last FMU of the plurality of FMUs of the value.

16 . The data storage device of claim 12 , wherein the checksum signature for each of the two or more consecutive adjacent FMUs has a same size.

17 . The data storage device of claim 12 , wherein the checksum signature for each of the two or more consecutive adjacent FMUs has a variable size.

18 . The data storage device of claim 12 , wherein the two or more consecutive adjacent FMUs comprises each previous FMU to a current FMU of the two or more consecutive adjacent FMUs.

19 . A data storage device, comprising:
means to store data; and a controller coupled to the means to store data, wherein the controller is configured to:
generate a checksum signature for each flash management unit (FMU) of a value of a key value (KV) pair data, wherein:
the KV pair data comprises a key and the value;
the key addresses the value;
the value comprises a plurality of FMUs; and
the checksum signature generated for each of the FMUs other than a first FMU of the plurality of FMUs is associated with a current FMU and each previous FMU of the plurality of FMUs;

program the value and each checksum signature to the means to store data;
receive a read request comprising the key from a host device;
retrieve the value and a checksum signature associated with an FMU requested by the read request from the means to store data;
generate another checksum signature for the retrieved value, wherein the another checksum signature is associated with the FMU requested and each previous FMU relative to the FMU requested;
determine that the another checksum signature matches the checksum signature retrieved; and
provide the value to the host device.

20 . The data storage device of claim 19 , wherein each checksum signature generated for each of the FMUs other than a first FMU of the plurality of FMUs comprises either:
a constant size; or a variable size.

Assignees

• Western Digital Tech Inc

Inventors

• Bazarsky Alexander
• Avraham David
• Zamir Ran

Classifications

• G06F21/64 Primary

  Protecting data integrity, e.g. using checksums, certificates or signatures · CPC title

• G06F21/79

  in semiconductor storage media, e.g. directly-addressable memories · CPC title

• G06F21/602 Primary

  Providing cryptographic facilities or services · CPC title