Array substrate, liquid crystal display panel and liquid crystal display device

US2025035995A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2025035995-A1
Application numberUS-202418911511-A
CountryUS
Kind codeA1
Filing dateOct 10, 2024
Priority dateJul 29, 2020
Publication dateJan 30, 2025
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The present disclosure provides an array substrate, a liquid crystal display panel and a liquid crystal display device, including: a base substrate; gate lines each extending in a first direction on the base substrate; data lines each extending in a second direction intersecting the first direction; pixel units located in regions defined by the gate lines and the data lines; each pixel unit has a first side and a second side each extending in the second direction and opposite to each other in the first direction; each pixel unit includes a first electrode including a plurality of strip-shaped 10 electrodes, at least part of the strip-shaped electrodes each have a first part and a second part extending in different directions, first parts are connected at the first side, second parts are disconnected at the second side, and lengths of the first part and the second part are different.

First claim

Opening claim text (preview).

What is claimed is: 1 . An array substrate, comprising: a base substrate; a plurality of gate lines each extending in a first direction on the base substrate; a plurality of data lines each extending in a second direction intersecting the first direction; a plurality of pixel units located in regions defined by the gate lines and the data lines, wherein each pixel unit has a first side and a second side each extending in the second direction and opposite to each other in the first direction, each pixel unit comprises a first electrode, the first electrode comprises a plurality of strip-shaped electrodes, at least part of the strip-shaped electrodes each have a first part and a second part extending in different directions, first parts are connected at the first side, second parts are disconnected at the second side, and lengths of the first part and the second part are different, wherein the strip-shaped electrodes each extend along a third direction and are arranged along a fourth direction intersecting the third direction; the first electrode further comprises a connection electrode, the connection electrode comprises a first connection electrode, a second connection electrode and a third connection electrode, the first connection electrode and the second connection electrode each extend in the first direction and are arranged in the second direction, and the third connection electrode is connected to the first connection electrode and the second connection electrode at the first side; each first part is connected to the first connection electrode or the third connection electrode; each strip-shaped electrode is connected between the second connection electrode and the third connection electrode and is not overlapped with the second side, and a length of an orthographic projection of each strip-shaped electrode in the first direction is less than a distance between the first side and the second side. 2 . The array substrate of claim 1 , wherein an included angle between the direction in which each first part extends and the direction in which each second part extends is greater than about 0° and less than or equal to about 45°. 3 . The array substrate of claim 1 , wherein each first part is in a shape of a straight line, and each second part is in a shape of a curved line that is curved away from the direction in which each first part extends, and at least a portion of the second parts have a same radian. 4 . The array substrate of claim 1 , wherein a line width of each first part is the same as a line width of each second part. 5 . The array substrate of claim 1 , wherein a farthest end of each second part away from the first part is of a round angle. 6 . The array substrate of claim 1 , wherein the strip-shaped electrodes comprises a plurality of first strip-shaped electrodes and a plurality of second strip-shaped electrodes, a direction in which the first strip-shaped electrodes each extend is different from a direction in which the second strip-shaped electrodes each extend. 7 . The array substrate of claim 6 , wherein the first strip-shaped electrodes and the second strip-shaped electrodes are symmetrical with respect to the first direction. 8 . The array substrate of claim 7 , wherein an included angle between the first strip-shaped electrodes and the second strip-shaped electrodes is greater than or equal to about 80° and less than or equal to about 100°, or an included angle between the first strip-shaped electrodes and the second strip-shaped electrodes is greater than about 0° and less than or equal to about 10°. 9 . The array substrate of claim 7 , wherein each of the second parts is bent toward a side away from a symmetry axis of the first strip-shaped electrodes and the second strip-shaped electrodes, or each of the second parts is bent toward a side close to a symmetry axis of the first strip-shaped electrodes and the second strip-shaped electrodes. 10 . The array substrate of claim 9 , wherein a distance between each strip-shaped electrode and the symmetry axis gradually decreases from an end of the strip-shaped electrode close to the first side to an end of the strip-shaped electrode close to the second side. 11 . The array substrate of claim 1 , wherein for the first strip-shaped electrodes and the second strip-shaped electrodes having orthographic projections each with a length in the first direction less than a distance between the first side and the second side and not overlapping with the second side, ends of the first strip-shaped electrode and the second strip-shaped electrode symmetrical with respect to a perpendicular bisector of the third connection electrode are connected, and another ends of the first strip-shaped electrode and the second strip-shaped electrode are connected to the third connection electrode; the first part of each first strip-shaped electrode is connected to the first connection electrode or the third connection electrode, and the first part of each second strip-shaped electrode is connected to the second connection electrode or the third connection electrode. 12 . The array substrate of claim 9 , wherein a distance between each strip-shaped electrode and the symmetry axis gradually increases from an end of the strip-shaped electrode close to the first side to an end of the strip-shaped electrode close to the second side. 13 . The array substrate of claim 12 , wherein the connection electrode further comprises a fourth connection electrode, the fourth connection electrode extends in the first direction and is arranged in the second direction, and the third connection electrode is further connected to the fourth connection electrode at the first side. 14 . The array substrate of claim 13 , wherein for the first strip-shaped electrodes and the second strip-shaped electrodes having orthographic projections each with a length in the first direction less than a distance between the first side and the second side and not overlapping the second side, each first strip-shaped electrode is connected between the first connection electrode and the third connection electrode, and each second strip-shaped electrode is connected between the second connection electrode and the third connection electrode; the first part of each first strip-shaped electrode is connected to the third connection electrode or the fourth connection electrode; the first part of each second strip-shaped electrode is connected to the third connection electrode or the fourth connection electrode. 15 . The array substrate of claim 1 , wherein each pixel unit further comprises a second electrode between the first electrode and the base substrate or on a side of the first electrode away from the base substrate, and the second electrode is a planar electrode. 16 . The array substrate of claim 15 , wherein an orthographic projection of the first electrode on the base substrate is within an orthographic projection of the second electrode on the base substrate, and wherein a distance between a boundary of the orthographic projection of the second electrode on the base substrate and an orthographic projection of the data line adjacent to the second electrode on the base substrate is less than a distance between a boundary of the orthographic projection of the first electrode on the base substrate and an orthographic projection of the data line adjacent to the first electrode on the base substrate. 17 . The array substrate of claim 1 , further comprising a first alignment layer on a side, away from the base substrate, of a layer where the pix

Assignees

Inventors

Classifications

  • Interconnections, e.g. scanning lines · CPC title

  • wherein the TFTs are in active matrices · CPC title

  • Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element · CPC title

  • Colour filters incorporated in the active matrix substrate · CPC title

  • for fringe field switching [FFS] where the common electrode is not patterned · CPC title

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What does patent US2025035995A1 cover?
The present disclosure provides an array substrate, a liquid crystal display panel and a liquid crystal display device, including: a base substrate; gate lines each extending in a first direction on the base substrate; data lines each extending in a second direction intersecting the first direction; pixel units located in regions defined by the gate lines and the data lines; each pixel unit has…
Who is the assignee on this patent?
Boe Technology Group Co Ltd
What technology area does this patent fall under?
Primary CPC classification G02F1/133707. Mapped technology areas include Physics.
When was this patent published?
Publication date Thu Jan 30 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).