Manufacturing method of display device

Patent metadata

Field	Value
Publication number	US-2025031518-A1
Application number	US-202418626500-A
Country	US
Kind code	A1
Filing date	Apr 4, 2024
Priority date	Jul 19, 2023
Publication date	Jan 23, 2025
Grant date	—

Abstract

A manufacturing method of a display device includes preparing a substrate including a metal pattern, forming a first active pattern disposed on the substrate and including first and second areas and a first channel area between the first and second areas, forming a first gate electrode pattern on the first active pattern, forming a second active pattern on the first gate electrode pattern, forming an etch stop pattern overlapping the first and second areas, forming an inter-insulating layer covering the etch stop pattern, defining a first hole exposing the etch stop pattern and a second hole exposing the inter-insulating layer, defining a third hole exposing a top surface of the substrate, defining a fourth hole penetrating the etch stop pattern and a fifth hole exposing the metal pattern, forming a metal pattern connection electrode on the metal pattern, and forming a light-emitting device on the metal pattern connection electrode.

First claim

What is claimed is:

1 . A manufacturing method of a display device, the method comprising:
preparing a substrate which includes a metal pattern and in which a display area and a non-display area are defined; forming a first active pattern disposed on the substrate and including a first area, a second area, and a first channel area disposed between the first area and the second area; forming a first gate electrode pattern overlapping the first channel area on the first active pattern; forming a second active pattern on the first gate electrode pattern; forming an etch stop pattern in a same layer as the second active pattern and overlapping the first area and the second area of the first active pattern; forming an inter-insulating layer covering the etch stop pattern; defining a first hole exposing the etch stop pattern and a second hole exposing the inter-insulating layer; defining a third hole extended to the second hole and exposing a top surface of the substrate; defining a fourth hole extended to the first hole and penetrating the etch stop pattern and a fifth hole extended to the third hole and exposing the metal pattern; forming a metal pattern connection electrode disposed on the metal pattern and connected to the metal pattern through the fifth hole; and forming a light-emitting device on the metal pattern connection electrode.

2 . The method of claim 1 , wherein the forming the substrate comprising:
forming a first base substrate on a carrier substrate; forming the metal pattern on the first base substrate; and forming a second base substrate on the first base substrate and the metal pattern.

3 . The method of claim 2 , wherein the third hole exposes a top surface of the second base substrate.

4 . The method of claim 2 , wherein the first base substrate and the second base substrate include plastic with flexible characteristics.

5 . The method of claim 4 , wherein the first base substrate and the second base substrate include polyimide.

6 . The method of claim 2 , further comprising:
removing the carrier substrate after the forming the light-emitting device.

7 . The method of claim 1 , further comprising:
forming a first insulating layer covering the first active pattern after the forming the first active pattern; and forming a second insulating layer covering the first gate electrode pattern after the forming the first gate electrode pattern.

8 . The method of claim 7 , wherein an etch rate of the first insulating layer, an etch rate of the second insulating layer, and an etch rate of the inter-insulating layer are smaller than an etch rate of the etch stop pattern.

9 . The method of claim 8 , wherein when each of the first insulating layer, the second insulating layer, and the inter-insulating layer includes an inorganic material, an etch selectivity between at least one of the first insulating layer, the second insulating layer and the inter-insulating layer including the inorganic material and the etch stop pattern is about 1:15 or more.

10 . The method of claim 8 , wherein when each of the first insulating layer, the second insulating layer, and the inter-insulating layer includes an organic material, an etch selectivity between at least one of the first insulating layer, the second insulating layer and the inter-insulating layer including the organic material and the etch stop pattern is about 1:1000 or more.

11 . The method of claim 1 , wherein the first active pattern and the second active pattern include different materials from each other.

12 . The method of claim 1 , wherein the first active pattern includes a silicon semiconductor.

13 . The method of claim 1 , wherein the etch stop pattern and the second active pattern are formed simultaneously.

14 . The method of claim 13 , wherein the etch stop pattern and the second active pattern includes a same oxide semiconductor.

15 . The method of claim 14 , wherein the etch stop pattern and the second active pattern includes indium-gallium-zinc-oxide (“IGZO”).

16 . The method of claim 1 , wherein the fifth hole is defining in the display area.

17 . The method of claim 1 , wherein the fifth hole is defining in the non-display area.

Assignees

• Samsung Display Co Ltd

Inventors

• JEON Bogeon

Classifications

• H10K59/18 Primary

  Tiled displays · CPC title

• H10K71/00

  Manufacture or treatment specially adapted for the organic devices covered by this subclass · CPC title

• H10K59/1201 Primary

  Manufacture or treatment · CPC title

• G09F9/302 Primary

  characterised by the form or geometrical disposition of the individual elements · CPC title

• H10K59/131

  Interconnections, e.g. wiring lines or terminals · CPC title