Circuit with a phase locked loop with disturbance responses

Patent metadata

Field	Value
Publication number	US-2025030427-A1
Application number	US-202318524711-A
Country	US
Kind code	A1
Filing date	Nov 30, 2023
Priority date	Jul 18, 2023
Publication date	Jan 23, 2025
Grant date	—

Abstract

A circuit for a phase-locked loop is described herein. The circuit includes a phase frequency detector configured to determine a phase error, a loop filter coupled to the phase frequency detector and configured to provide a clock control signal based on the phase error, and a controller coupled to the phase frequency detector and to the loop filter. The controller is configured to receive the phase error, detect a behavior of the phase error, and, responsive to the behavior of the phase error, perform a response that includes causing the phase frequency detector to adjust the phase error and causing the loop filter to adjust the clock control signal. Thus, the circuit may reduce settling time, overshoot, and/or undershoot in an output clock generated based on the clock control signal.

First claim

What is claimed is:

1 . A circuit comprising:
a phase frequency detector configured to determine a phase error; a loop filter coupled to the phase frequency detector and configured to provide a clock control signal based on the phase error; and a controller coupled to the phase frequency detector and to the loop filter, the controller configured to:
receive the phase error;
detect a behavior of the phase error; and
responsive to the behavior of the phase error, perform a response that includes:
causing the phase frequency detector to adjust the phase error; and
causing the loop filter to adjust the clock control signal.

2 . The circuit of claim 1 , wherein the causing of the phase frequency detector to adjust the phase error includes causing the phase frequency detector to determine the phase error by limiting a measured phase error to a range.

3 . The circuit of claim 2 , wherein the range is between- 0 . 5 periods and 0 . 5 periods.

4 . The circuit of claim 2 , wherein the adjusted phase error is whichever of the measured phase error minus a floor of the measured phase error or the measured phase error minus a ceiling of the measured phase error has a lesser magnitude.

5 . The circuit of claim 1 , wherein:
the loop filter includes an integrator; and the causing of the loop filter to adjust the clock control signal includes setting an output of the integrator to a previous value of the clock control signal minus a function of the phase error.

6 . The circuit of claim 1 , wherein the causing of the phase frequency detector to adjust the phase error includes causing the phase frequency detector to set the phase error to a predetermined value.

7 . The circuit of claim 6 , wherein the predetermined value is zero.

8 . The circuit of claim 1 , wherein:
the loop filter includes an integrator; and the causing of the loop filter to adjust the clock control signal includes setting an output of the integrator to a previous value of the clock control signal.

9 . The circuit of claim 1 , wherein the controller is configured to select the response from among a set of responses.

10 . The circuit of claim 1 , wherein the behavior includes one of: the phase error exceeding a threshold for a given duration, the phase error monotonically increasing for a given duration, or the phase error monotonically increasing for a given duration then decreasing.

11 . A circuit comprising:
a phase locked loop circuit that includes:
a phase frequency detector configured to:
receive a reference clock and a feedback clock; and
determine a phase error based on the reference clock and the feedback clock;

a loop filter coupled to the phase frequency detector and configured to provide a clock control signal based on the phase error; and
an oscillator coupled to the loop filter and configured to provide a clock signal based on the clock control signal, wherein the feedback clock is based on the clock signal, and wherein the phase locked loop circuit is configured to provide an output clock based on the clock signal; and
a controller coupled to the phase locked loop circuit and configured to:
receive the phase error;
detect a behavior of the phase error; and
responsive to the behavior of the phase error, perform a response that includes:
causing the phase frequency detector to adjust the phase error; and
causing the loop filter to adjust the clock control signal.

12 . The circuit of claim 11 , wherein the response includes causing the phase frequency detector to wrap the phase error to a nearest clock edge.

13 . The circuit of claim 11 , wherein the response includes causing the phase frequency detector to adjust the phase error by limiting a measured phase error to a range.

14 . The circuit of claim 13 , wherein the response includes causing the phase frequency detector to adjust the phase error based on whichever of the measured phase error minus a floor of the measured phase error or the measured phase error minus a ceiling of the measured phase error has a lesser magnitude.

15 . The circuit of claim 11 , wherein:
the loop filter includes an integrator; and the response includes setting an output of the integrator to a previous value of the clock control signal minus a function of the phase error.

16 . The circuit of claim 11 , wherein the response includes causing the phase frequency detector to set the phase error to a predetermined value.

17 . The circuit of claim 16 , wherein the predetermined value is zero.

18 . The circuit of claim 11 , wherein:
the loop filter includes an integrator; and the response includes setting an output of the integrator to a previous value of the clock control signal.

19 . The circuit of claim 11 , wherein the controller is configured to select the response from among a set of responses.

20 . The circuit of claim 11 , wherein:
the phase locked loop circuit includes a clock divider coupled to the oscillator and to the phase frequency detector; and the clock divider is configured to provide the feedback clock and the output clock based on the clock signal of the oscillator.

21 . The circuit of claim 11 , wherein the phase frequency detector is configured to:
receive a frequency control word; and determine the phase error further based on the frequency control word.

22 . A method comprising:
receiving a phase error with respect to a reference clock and a feedback clock, wherein:
the phase error is determined by a phase frequency detector; and
the feedback clock is generated based on an output of a loop filter;
detecting whether a behavior of the phase error is present; and based on whether the behavior is present, determine whether to perform a response that includes:
causing the phase frequency detector to adjust the phase error; and
causing the loop filter to adjust the output of the loop filter.

23 . The method of claim 22 further comprising performing the response, wherein the response includes causing the phase frequency detector to adjust the phase error by limiting a measured phase error to a range.

24 . The method of claim 23 , wherein the adjusted phase error is whichever of the measured phase error minus a floor of the measured phase error or the measured phase error minus a ceiling of the measured phase error has a lesser magnitude.

25 . The method of claim 22 further comprising performing the response, wherein:
the loop filter includes an integrator; and
the response includes setting an output of the integrator to a previous value of the output of the loop filter minus a function of the phase error.

26 . The method of claim 22 further comprising performing the response, wherein the response includes causing the phase frequency detector to set the phase error to a predetermined value.

27 . The method of claim 22 further comprising performing the response, wherein:
the loop filter includes an integrator; and
the response includes setting an output of the integrator to a previous value of the output of the loop filter.

28 . The method of claim 22 further comprising:
selecting the response from among a set of responses; and
performing the response.

29 . The method of claim 22 , wherein the behavior includes at least one of: the phase error exceeding a threshold for a given duration, the

Assignees

• Texas Instruments Inc

Inventors

• Moe Marius
• Graf Hagen
• Aaberge Tarjei

Classifications

• H03L7/1075

  by changing characteristics of the loop filter, e.g. changing the gain, changing the bandwidth (H03L7/1072 takes precedence) · CPC title

• H03L7/085

  concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00) · CPC title

• H03L7/093 Primary

  using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) · CPC title

• H03L7/0891

  the up-down pulses controlling source and sink current generators, e.g. a charge pump · CPC title

• H03L7/0991

  the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider (H03L7/0995 takes precedence; fixed oscillators with means for selecting among various phases H03L7/0814) · CPC title