Semiconductor device and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-2025022950-A1
Application number	US-202318524202-A
Country	US
Kind code	A1
Filing date	Nov 30, 2023
Priority date	Jul 13, 2023
Publication date	Jan 16, 2025
Grant date	—

Abstract

An embodiment semiconductor device includes a conductive region extending in a first direction and a second direction intersecting the first direction and stacked in a third direction intersecting the first direction and the second direction and a termination region at an end of the conductive region in the first direction, wherein the termination region includes an n+ type substrate, an n− type layer disposed on an upper surface of the n+ type substrate and having a plurality of first trenches opening upward in the third direction, and a lower gate runner covering the plurality of first trenches and disposed on an upper surface of the n− type layer.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a conductive region extending in a first direction and a second direction intersecting the first direction and stacked in a third direction intersecting the first direction and the second direction; and a termination region at an end of the conductive region in the first direction, wherein the termination region comprises:
an n+ type substrate;
an n− type layer disposed on an upper surface of the n+ type substrate and having a plurality of first trenches opening upward in the third direction; and
a lower gate runner covering the plurality of first trenches and disposed on an upper surface of the n− type layer.

2 . The semiconductor device of claim 1 , wherein a first direction spacing between the first trenches is less than or equal to a first direction width of each of the first trenches.

3 . The semiconductor device of claim 1 , wherein the lower gate runner comprises:
an upper portion covering the plurality of first trenches and disposed on an upper surface of the plurality of first trenches; and extended portions disposed inside each of the first trenches.

4 . The semiconductor device of claim 3 , wherein each of the extended portions comprises:
a trench sidewall portion disposed on a sidewall of the first trenches; and a trench bottom portion disposed on a bottom of the first trenches.

5 . The semiconductor device of claim 4 , wherein:
the trench sidewall portion has a convex shape toward an inside of the first trenches as it moves upward in the third direction; and the trench bottom portion has a convex shape toward the inside of the first trenches.

6 . The semiconductor device of claim 5 , wherein each of the first trenches has an empty space inside surrounded by an upper portion of the lower gate runner, the trench sidewall portion, and the trench bottom portion.

7 . The semiconductor device of claim 6 , wherein the empty space has a shape whose width in the first direction becomes narrower as it moves upward in the third direction.

8 . The semiconductor device of claim 1 , wherein the conductive region comprises:
the n+ type substrate; an n− type layer disposed on the upper surface of the n+ type substrate and having a second trench opening upward in the third direction; a p type region disposed within the n− type layer and disposed on a side of the second trench; a gate electrode disposed within the second trench; and a source electrode and a drain electrode disposed insulated from the gate electrode.

9 . The semiconductor device of claim 8 , wherein the gate electrode is disposed only inside the second trench and does not protrude outside the second trench in the third direction.

10 . The semiconductor device of claim 8 , wherein a ratio of a first direction width of each of the first trenches to a first direction width of the second trench is less than or equal to about 0.9.

11 . The semiconductor device of claim 8 , wherein:
a first direction width of the second trench is greater than or equal to about 0.1 μm; a third direction depth of the second trench is greater than or equal to about 0.5 μm; the first direction width of each of the first trenches is about 0.1 μm to about 2 μm; and the third direction depth of each of the first trenches is greater than or equal to about 0.3 μm.

12 . A semiconductor device comprising:
a conductive region extending in a first direction and a second direction intersecting the first direction and stacked in a third direction intersecting the first direction and the second direction; and a termination region at an end of the conductive region in the first direction,
wherein the termination region comprises:
an n+ type substrate;
an n− type layer disposed on an upper surface of the n+ type substrate;
a buffer layer disposed on an upper surface of the n− type layer and having a plurality of first trenches opening upward in the third direction; and
a lower gate runner covering the plurality of first trenches and disposed on an upper surface of the buffer layer.

13 . The semiconductor device of claim 12 , wherein a first direction spacing between the first trenches is less than or equal to a first direction width of each of the first trenches.

14 . The semiconductor device of claim 12 , wherein the lower gate runner comprises:
an upper portion covering the plurality of first trenches and disposed on an upper surface of the plurality of first trenches; and extended portions disposed inside each of the first trenches.

15 . The semiconductor device of claim 12 , wherein the conductive region comprises:
the n+ type substrate; an n− type layer disposed on the upper surface of the n+ type substrate and having a second trench opening upward in the third direction; a p type region disposed within the n− type layer and disposed on a side of the second trench; a gate electrode disposed within the second trench; and a source electrode and a drain electrode disposed insulated from the gate electrode.

16 . A method of manufacturing a semiconductor device, the method comprising:
forming an n− type layer on an upper surface of an n+ type substrate; forming a plurality of first trenches in the n− type layer, the plurality of first trenches opening upward toward an upper surface of the n− type layer; forming a preliminary gate electrode layer covering the plurality of first trenches and an upper portion of the n− type layer without filling all of an interior of the plurality of first trenches using a deposition method with a non-conformal step coverage; and etching a portion of the preliminary gate electrode layer that covers the n− type layer to form a lower gate runner that covers the plurality of first trenches and is disposed on the upper surface of the n− type layer.

17 . The method of claim 16 , wherein a first direction thickness of the portion covering the n-type layer of the preliminary gate electrode layer is about 0.5 times or more than a second direction width of each of the plurality of first trenches.

18 . The method of claim 16 , wherein the deposition method with a non-conformal step coverage comprises a plasma-enhanced chemical vapor deposition (PECVD) method using a thermal evaporator.

19 . The method of claim 16 , further comprising:
forming a second trench in the n− type layer, the second trench opening upward toward the upper surface of the n− type layer; forming the preliminary gate electrode layer that fills an inside of the second trench and covers the n− type layer using the deposition method with the non-conformal step coverage; etching a second portion of the preliminary gate electrode layer that covers the n− type layer until an upper surface of the preliminary gate electrode layer is disposed inside the second trench to form a gate electrode inside the second trench; and forming a source electrode and a drain electrode each to be insulated from the gate electrode.

20 . The method of claim 19 , wherein:
forming the second trench is performed while forming the plurality of first trenches; forming the preliminary gate electrode layer comprises forming the preliminary gate electrode layer covering the plurality of first trenches, filling all of the inside of the second trench, and covering the n− type layer without filling all of the interior of the plurality of first trenches; and etching the second portion of the preliminary gate electrode layer that covers the n− type layer until the upper s

Assignees

• Hyundai Motor Co Ltd
• Kia Corp

Inventors

• Park Junghee
• Chun Dae Hwan
• Hong Jungyeop
• Jung Youngkyun
• Joo Nackyong

Classifications

• H10D64/518

  characterised by their lengths or sectional shapes · CPC title

• H10D62/105

  by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  (IGFETs having LDD or drain extension regions H10D30/601) · CPC title

• H10D30/0297

  using recessing of the gate electrodes, e.g. to form trench gate electrodes · CPC title

• H10D64/01

  Manufacture or treatment · CPC title

• H10D62/106

  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions · CPC title