Semiconductor device and control method thereof

Patent metadata

Field	Value
Publication number	US-2025021701-A1
Application number	US-202418767433-A
Country	US
Kind code	A1
Filing date	Jul 9, 2024
Priority date	Jul 14, 2023
Publication date	Jan 16, 2025
Grant date	—

Abstract

To provide a semiconductor device and a control method for a semiconductor device that realizes high-speed processing. The semiconductor device includes a storage unit, an encryption processing unit, and a hash processing unit. The data stored in the storage unit is transferred to the encryption processing unit for each pre-calculation data of the first calculation unit, the encryption processing unit applies the calculation processing to generate post-calculation data. The generated first calculation unit of the post-calculation data is transferred to the hash processing unit, the hash processing unit applies the hash calculation process to the post-calculation data of the second calculation unit. The post-calculation data is transferred to the storage unit, and the calculation processing and the hash calculation processing are performed in parallel.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a memory circuit configured to store at least one of plaintext and ciphertext; an encryption processing circuit configured to perform crypt processing including encryption of the plaintext and decryption of the ciphertext; a hash processing circuit including a buffer, the hash processing circuit being configured to perform hash calculation processing to calculate a hash value, wherein the semiconductor device is configured to transfer pre-calculation data including at least one of the plaintext and the ciphertext to the encryption processing circuit for each first calculation unit of the encryption processing circuit, wherein the encryption processing circuit is configured to apply the crypt processing to the transferred first calculation unit of the pre-calculation data, generate the first unit of calculated data, and transfer the calculated data to the hash processing circuit, wherein the hash processing circuit is configured to store the transferred the calculated data for each first calculation unit to the buffer, apply the hash calculation processing to the calculated data for each second calculation unit, generate a hash value, and transfer the generated hash value to the memory circuit, wherein the semiconductor device is configured to transfer the first unit or the second unit of the calculated data to the memory circuit, wherein the crypt processing and the hash calculation process are configured to be performed in parallel, wherein the crypt processing, the hash calculation process and the transfer of the calculated data to the memory circuit are performed repeatedly in multiple times, and wherein the hash value transferred to the memory circuit corresponds the calculated data.

2 . The semiconductor device according to claim 1 , further comprising:
a bus configured to connect the memory circuit, the encryption processing circuit and the hash processing circuit to communicate each other; an alternative connection path configured to connect the encryption processing circuit and the hash processing circuit to communicate each other, wherein the calculated data generated in the encryption processing circuit is transferred to the bus and the alternative connection path, wherein the hash calculation process of the hash processing circuit is applied to the calculated data received via the alternative connection path.

3 . The semiconductor device according to claim 2 , further configured to switch a transfer mode between a first mode and a second mode,
wherein the first mode is that the encryption processing circuit transfers the calculated data only via the bus, wherein the second mode is that the encryption processing circuit transfers the calculated data via the bus and the alternative connection path.

4 . The semiconductor device according to claim 2 , further configured to switch a hash processing mode between a third mode and a fourth mode,
wherein the third mode is that the hash processing circuit applies the hash calculation process to the calculated data received via the bus, wherein the fourth mode is that the hash processing circuit applies the hash calculation process to the calculated data received via the alternative connection path.

5 . The semiconductor device according to claim 4 ,
wherein the hash processing circuit includes a detecting circuit configured to detect a status of the buffer and output a waiting signal to the encryption processing circuit when the status indicates that the buffer is not capable of store the calculated data, wherein the encryption processing circuit includes a controller circuit configured to, when the waiting signal is received, stop the transfer of calculated data to at least one of the bus or the alternative connection path.

6 . The semiconductor device according to claim 2 ,
wherein the bus comprises a first and a second bus, wherein the first bus is configured to transfer the pre-calculation data from the memory circuit to the encryption processing circuit, wherein the second bus is configured to transfer the calculated data from the encryption processing circuit to the memory circuit.

7 . The semiconductor device according to claim 1 , further comprising:
a bus configured to connect the memory circuit, the encryption processing circuit and the hash processing circuit to communicate each other, wherein the encryption processing circuit includes a plurality of bus ports configured to input of the pre-calculation data and output of the calculated data with the bus, wherein the bus ports include a first bus port and a second bus port, wherein the calculated data outputted via the first bus port are transferred to the memory circuit, wherein the calculated data outputted via the second bus port are transferred to the hash processing circuit, wherein the hash processing circuit applies the hash calculation processing to the calculated data received via the second bus port and the bus.

8 . The semiconductor device according to claim 7 , further configured to switch a transfer mode between a first mode and a second mode,
wherein the first mode is that the encryption processing circuit transfers the calculated data only via either one of the first bus port or the second bus port, wherein the second mode is that the encryption processing circuit transfers the calculated data via the first bus port and the second bus port.

9 . The semiconductor device according to claim 7 ,
wherein the bus comprises a first and a second bus, wherein the first bus is configured to transfer the pre-calculation data from the memory circuit to the encryption processing circuit, and transfer the calculated data from the encryption processing circuit to the hash processing circuit, wherein the second bus is configured to transfer the calculated data from the encryption processing circuit to the memory circuit.

10 . The semiconductor device according to claim 1 , further comprises:
a transfer circuit configured to perform the transfer of the pre-calculation data and the calculated data, a control circuit configured to control the memory circuit, the encryption processing circuit and the hash processing circuit.

11 . A method for encryption processing comprising:
(a) transfer pre-calculation data from a memory device to an encryption processing device for each first processing unit; (b) generate the first processing unit of calculated data by performing an encryption process with the first processing unit of the pre-calculation data; (c) transfer the calculated data to a hash processing device; (d) store the first processing unit of the calculated data to a buffer of the hash processing device; (e) generate hash value by performing a hash processing with a second processing unit of the calculated data stored in the buffer of the hash processing device; (f) transfer the first or second processing unit of the calculated data to the memory device; (g) store the hash value corresponding the calculated data, wherein (b) and (e) are performed in parallel, and wherein (a), (b), (c), (d) and (e) are performed repeatedly in multiple times.

12 . The method for encryption processing according to claim 11 ,
wherein (c) is performed by outputting the first processing unit of the calculated data to a connection path which is configured to communicate from the encryption processing device to the hash processing device, wherein (f) is performed by outputting the first processing unit of the calculated data to a bus which is configured to communicate in bi-direction between memory device, the encryption processing device an

Assignees

• Renesas Electronics Corp

Inventors

• Ito Kenichi

Classifications

• G06F21/72 Primary

  in cryptographic circuits · CPC title

• G06F21/85

  interconnection devices, e.g. bus-connected or in-line devices · CPC title

• G06F21/79 Primary

  in semiconductor storage media, e.g. directly-addressable memories · CPC title