Merged Power Delivery

Patent metadata

Field	Value
Publication number	US-2025015701-A1
Application number	US-202418893579-A
Country	US
Kind code	A1
Filing date	Sep 23, 2024
Priority date	Aug 16, 2022
Publication date	Jan 9, 2025
Grant date	—

Abstract

A power delivery sub-system included in a computer system employs a primary voltage regulator circuit that generates a primary supply voltage on a primary power supply node. The power delivery sub-system also includes multiple bypass voltage regulator circuits that source corresponding bypass currents to a local power supply nodes in an integrated circuit. The integrated circuit includes multiple circuit blocks coupled to corresponding ones of the local power supply nodes, and multiple local voltage regulator circuits coupled to the primary power supply node. When a voltage level of a given local power supply node drops below a threshold value, a corresponding local voltage regulator circuit sources a supply current to the given local power supply node.

First claim

What is claimed is:

1 . An apparatus, comprising:
an integrated circuit including:
a functional circuit block coupled to a local power supply node; and
a local voltage regulator circuit coupled to the functional circuit block via the local power supply node; and
a bypass voltage regulator circuit coupled to the local power supply node and configured to provide a particular voltage level to the local power supply node; and wherein:
to provide the particular voltage level, the bypass voltage regulator circuit is configured to source a bypass electrical current to the local power supply node;
the local voltage regulator circuit is configured to maintain the particular voltage level; and
to maintain the particular voltage level, the local voltage regulator circuit is configured to source a supply electrical current to the local power supply node in response to a determination that a voltage level at the local power supply node fails to satisfy a threshold voltage value.

2 . The apparatus of claim 1 , wherein:
a change in a load current drawn by the functional circuit block induces a drop in voltage level, causing the voltage level to fail to satisfy the threshold voltage value; the bypass voltage regulator circuit is unable to adjust the voltage level to compensate for the drop; and the local voltage regulator circuit is configured to source the supply current in response to detection of the drop in the voltage level.

3 . The apparatus of claim 1 , wherein the bypass voltage regulator circuit includes:
a control circuit configured to generate a control signal; a switching circuit coupled to the control circuit and coupled to an input power supply node; and a resistor coupled between a first node and a second node; and wherein:
the control signal is configured to generate the control signal based on a voltage difference between a first voltage level of the first node and a second voltage level of the second node; and
the switching circuit is configured to generate the bypass electrical current based on a supply voltage level of the input power supply node and the control signal indicating the voltage difference.

4 . The apparatus of claim 3 , wherein the switching circuit is one of a boost converter or a buck converter.

5 . The apparatus of claim 1 , wherein the local voltage regulator circuit includes a low-dropout regulator circuit, and wherein, to maintain the particular voltage level, the low-drop regulator circuit is configured to adjust a conductance between a primary power supply node and the local power supply node.

6 . The apparatus of claim 5 , wherein the low-dropout regulator circuit includes a power switch circuit configured to prevent injection of the bypass electrical current onto the local power supply node based on a control signal received at the power switch circuit.

7 . The apparatus of claim 1 , wherein the local voltage regulator circuit includes a switched-capacitor circuit, and wherein, to maintain the particular voltage level, the switched-capacitor circuit is configured to:
charge a capacitor of the switched-capacitor circuit using a primary supply voltage; and discharge the capacitor into the local power supply node.

8 . An apparatus, comprising:
an integrated circuit that includes:
a first regulator circuit coupled to a power converter circuit via a first auxiliary power supply node;
a first circuit block coupled to the first regulator circuit via a first local power supply node; and wherein:
the first regulator circuit is configured to generate a particular voltage level on the first local power supply node in response to a fall in a voltage level of the first local power supply node, the fall in the voltage level attributable to a fluctuation in an electrical current demand associated with the first circuit block.

9 . The apparatus of claim 8 , wherein the integrated circuit further comprises:
a second regulator circuit coupled to the power converter circuit via a second auxiliary power supply node; a second circuit block coupled to the second regulator circuit via a second local power supply node; and a selection circuit coupled to the first local power supply node and to the second local power supply node; and wherein:
the selection circuit is configured to generate a feedback signal based on a lowest voltage level of one of the first local power supply node or the second local power supply node; and
the power converter circuit is configured to adjust a magnitude of an electrical current output by the power converter circuit based on the feedback signal.

10 . The apparatus of claim 9 , further comprising the power converter circuit, and wherein the selection circuit includes a monitor circuit configured to:
monitor a first voltage level of the first local power supply node; monitor a second voltage level of the second local power supply node; and select a lower of the first voltage level or the second voltage level; and wherein:
the feedback signal is the lower of the first voltage level or the second voltage level; and the
monitor circuit is further configured to drive the feedback signal onto a pad.

11 . The apparatus of claim 10 , wherein the selection circuit further includes an electrostatic discharge circuit configured to clamp a voltage level on the pad during an electrostatic discharge event, and wherein the electrostatic discharge event includes a static charge that induces formation of an electrical current in the integrated circuit, the electrical current capable of damaging circuitry of the integrated circuit.

12 . The apparatus of claim 10 , wherein the monitor circuit includes:
a switch circuit coupled to the first local power supply node and to the second local power supply node, wherein the switch circuit is configured to generate a first signal based on the first voltage level and a second signal based on the second voltage level; a comparator circuit coupled to the switch circuit and to a timing circuit, wherein the comparator circuit is configured to generate a comparison signal based on the first signal, the second signal, and a phase signal received at the comparator circuit from the timing circuit; and a filter circuit coupled to the comparator circuit, wherein the filter circuit is configured to generate a filtered signal based on the comparison signal.

13 . The apparatus of claim 12 , further comprising:
a driver circuit coupled to the filter circuit and to one of the first local power supply node or the second local power supply node, wherein the driver circuit is configured to generate a selected voltage based at least on the filtered signal.

14 . The apparatus of claim 12 , wherein the monitor circuit further includes the timing circuit coupled to the comparator circuit, wherein the timing circuit is configured to generate the phase signal based on a clock signal, and wherein, to generate the comparison signal, the comparator circuit is configured to identify whether the first signal or the second signal has a smaller value based on a stream of samples included in the comparison signal, the stream of samples generated based on the phase signal.

15 . The apparatus of claim 12 , wherein:
the filter circuit is further configured to suppress spurious sense samples from the comparison signal; to suppress the spurious sense samples, a depth parameter and a latency parameter of the filter circuit are adjusted; the depth parameter includes a minimum quantity of the spurious sense samples to be suppressed; and the latency parameter includes a maximum quantity of opposite-polarity sam

Assignees

• Apple Inc

Inventors

• Uan-Zo-Li Alexander B
• Jiang Shuai
• Langlinais Jamie L
• Hammarlund Per H
• Yeager Hans L
• Zyuban Victor
• Kim Sung J
• Xu Wei
• Mandrekar Rohan U
• Narayan Sambasivan
• Abu-Rahma Mohamed H
• Raszka Jaroslav
• Bruckner Robert O

Classifications

• H02M3/1566

  with means for compensating against rapid load changes, e.g. with auxiliary current source, with dual mode control or with inductance variation · CPC title

• H02M1/008 Primary

  Plural converter units for generating at two or more independent and non-parallel outputs, e.g. systems with plural point of load switching regulators · CPC title