Switched-capacitor circuit and pipelined analog-to-digital convertor including the same

Patent metadata

Field	Value
Publication number	US-2025007396-A1
Application number	US-202418755688-A
Country	US
Kind code	A1
Filing date	Jun 27, 2024
Priority date	Jun 30, 2023
Publication date	Jan 2, 2025
Grant date	—

Abstract

A switched-capacitor circuit includes a sampling capacitor array, a control circuit, and a charge-transfer circuit. The sampling capacitor array is configured to sample an input voltage in a sampling phase. The control circuit is configured to determine magnitude of a preset voltage according to the input voltage, and configured to adjust the input voltage sampled by the sampling capacitor array in a preset phase according to magnitude of the input voltage to generate an adjusted voltage. The charge-transfer circuit is configured to amplify the adjusted voltage in a charge-transfer phase to generate an output voltage at an output terminal, and configured to provide the preset voltage to the output terminal in the preset phase.

First claim

What is claimed is:

1 . A switched-capacitor circuit, comprising:
a first sampling capacitor array, configured to sample a first input voltage in a sampling phase; a control circuit, configured to determine magnitude of a first preset voltage according to the first input voltage, and configured to adjust the first input voltage sampled by the first sampling capacitor array in a preset phase according to magnitude of the first input voltage, so as to generate a first adjusted voltage; and a charge-transfer circuit, configured to amplify the first adjusted voltage in a charge-transfer phase, so as to generate a first output voltage at a first output terminal, and configured to provide the first preset voltage to the first output terminal in the preset phase.

2 . The switched-capacitor circuit of claim 1 , further comprising:
a second sampling capacitor array, configured to sample a second input voltage in the sampling phase, wherein the control circuit is configured to determine the magnitude of the first preset voltage and magnitude of a second preset voltage according to an input voltage difference between the first input voltage and the second input voltage, and configured to adjust the second input voltage sampled by the second sampling capacitor array in the preset phase according to magnitude of the second input voltage, so as to generate a second adjusted voltage, wherein the charge-transfer circuit is configured to amplify the second adjusted voltage in the charge-transfer phase so as to generate a second output voltage at a second output terminal, and configured to provide the second preset voltage to the second output terminal in the preset phase, wherein a phase of the first preset voltage is opposite to a phase of the second preset voltage.

3 . The switched-capacitor circuit of claim 2 , wherein the control circuit comprises:
an analog-to-digital converter (ADC), configured to compare the input voltage difference with a plurality of voltage thresholds to determine a first voltage range including the input voltage difference from a plurality of voltage ranges, and configured to output a first digital code corresponding to the first voltage range, wherein the plurality of voltage ranges are identified by the plurality of voltage thresholds arranged in ascending order; and a decoder, configured to determine the magnitude of the first preset voltage and the magnitude of the second preset voltage according to the first digital code.

4 . The switched-capacitor circuit of claim 3 , wherein when the input voltage difference is in an M-th voltage range of the plurality of voltage ranges, the decoder is configured to set the first preset voltage to be smaller than the second preset voltage, wherein M is a positive integer; and
when the input voltage difference is in an (M+1)-th voltage range of the plurality of voltage ranges, the decoder is configured to set first preset voltage to be larger than the second preset voltage.

5 . The switched-capacitor circuit of claim 3 , wherein when the input voltage difference is in a P-th voltage range of the plurality of voltage ranges, the decoder is configured to set the first preset voltage to be smaller than the second preset voltage, wherein P is an odd number; and
when the input voltage difference is in a Q-th voltage range of the plurality of voltage ranges, the decoder is configured to set the first preset voltage to be larger than the second preset voltage, wherein Q is an even number.

6 . The switched-capacitor circuit of claim 2 , wherein the charge-transfer circuit comprises:
a comparator, configured to compare the first adjusted voltage with the second adjusted voltage, so as to generate a first control signal and a second control signal; a first charge pump controlled by the first control signal, configured to generate the first output voltage at the first output terminal; and a second charge pump controlled by the second control signal, configured to generate the second output voltage at the second output terminal, wherein the control circuit is configured to set the first charge pump as one of a current source and a current sink and set the second charge pump as the other one of the current source and the current sink, according to the input voltage difference.

7 . The switched-capacitor circuit of claim 1 , wherein the control circuit comprises:
an ADC, configured to compare the first input voltage with a plurality of voltage thresholds, so as to determine a first voltage range including the first input voltage from a plurality of voltage ranges, and configured to output a first digital code corresponding to the first voltage range, wherein the plurality of voltage ranges are identified by the plurality of voltage thresholds arranged in ascending order; and a decoder, configured to determine the magnitude of the first preset voltage according to the first digital code.

8 . The switched-capacitor circuit of claim 7 , wherein when the first input voltage is in an M-th voltage range of the plurality of the voltage ranges, the decoder is configured to set the first preset voltage to be smaller than a common voltage, wherein M is a positive integer; and
when the first input voltage is in an (M+1)-th voltage range of the plurality of the voltage ranges, the decoder is configured to set the first preset voltage to be larger than the common voltage.

9 . The switched-capacitor circuit of claim 7 , wherein when the first input voltage is in a P-th voltage range of the plurality of voltage ranges, the decoder is configured to set the first preset voltage to be smaller than a common voltage, wherein P is an odd number,
when the first input voltage is in a Q-th voltage range of the plurality of voltage ranges, the decoder is configured to set the first preset voltage to be larger than the common voltage, wherein Q is an even number.

10 . A switched-capacitor circuit, comprising:
a first sampling capacitor array, configured to sample a first input voltage in a sampling phase; a control circuit, configured to determine magnitude of a first reference voltage and magnitude of a first preset voltage according to a relationship between the first input voltage and a plurality of voltage thresholds, and configured to couple the first reference voltage to the first input voltage sampled by the first sampling capacitor array in a preset phase, so as to generate a first adjusted voltage; and a charge-transfer circuit, configured to amplify the first adjusted voltage in a charge-transfer phase, so as to generate a first output voltage at a first output terminal, and configured provide the first preset voltage to the first output terminal in the preset phase.

11 . The switched-capacitor circuit of claim 10 , further comprises:
a second sampling capacitor array, configured to sample a second input voltage in the sampling phase, wherein the control circuit is configured to compare an input voltage difference between the first input voltage and the second input voltage with the plurality of voltage thresholds, so as to determine the magnitude of the first reference voltage, the magnitude of the first preset voltage, magnitude of a second reference voltage and magnitude of a second preset voltage, and configured to couple the second reference voltage to the second input voltage sampled by the second sampling capacitor array in the preset phase, so as to generate a second adjusted voltage, wherein the charge-transfer circuit is configured to amplify the second adjusted voltage in the charge-transfer phase, so as to generate a second output voltage at a second output terminal, and configured to provide the second preset voltage

Assignees

• Realtek Semiconductor Corp

Inventors

• Hong Wei-Cian

Classifications

• H02M3/07 Primary

  using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} · CPC title

• H03M1/12 Primary

  Analogue/digital converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title