Transistor with channel-symmetric gate

Patent metadata

Field	Value
Publication number	US-2025006810-A1
Application number	US-202318216514-A
Country	US
Kind code	A1
Filing date	Jun 29, 2023
Priority date	Jun 29, 2023
Publication date	Jan 2, 2025
Grant date	—

Abstract

Transistor structures with gate material self-aligned to underlying channel material. A channel mask material employed for patterning channel material is retained during selective formation of a second mask material upon exposed surfaces of gate material. The channel mask material is then thinned to expose a sidewall of adjacent gate material. The exposed gate material sidewall is laterally recessed to expand an opening beyond an edge of underlying channel material. A third mask material may be formed in the expanded opening to protect an underlying portion of gate material during a gate etch that forms a trench bifurcating the underlying portion of gate material from an adjacent portion of gate material. The underlying portion of gate material extends laterally beyond the channel material by an amount that is substantially symmetrical about a centerline of the channel material and this amount has a height well controlled relative to the channel material.

First claim

What is claimed is:

1 . An integrated circuit (IC) structure, comprising:
a transistor over a plane of the IC structure, the transistor comprising:
a channel material of a first lateral width; and
a first portion of gate material adjacent to a sidewall of the channel material, the first portion of gate material extending a first height from the plane; and
a gate mask material over a second portion of the gate material directly above the channel material, the gate mask material having a second lateral width, larger than the first lateral width, wherein the second portion of the gate material extends a second height that is within 10 nm of the first height.

2 . The IC structure of claim 1 , wherein the second height is within 5 nm of the first height.

3 . The IC structure of claim 2 , wherein the second height is no greater than the first height.

4 . The IC structure of claim 1 , wherein a lateral width of the second portion of the gate material summed with twice the lateral width of the first portion of the gate material is smaller than the second lateral width, but larger than the first lateral width.

5 . The IC structure of claim 1 , further comprising an insulator material or an air gap bifurcating the first portion of the gate material from a third portion of the gate material that extends a third height, wherein the third height is more than 10 nm greater than the first height and the second height

6 . The IC structure of claim 1 , wherein a top surface of the third portion of the gate material is substantially coplanar with a top surface of a spacer dielectric material separating the first portion of the gate material from a source material or a drain material.

7 . The IC structure of claim 6 , wherein the IC structure further comprises an electrical routing feature comprising the third portion of the gate material.

8 . The IC structure of claim 1 , wherein a centerline of the channel material is substantially coincident with a centerline of the gate mask material.

9 . The IC structure of claim 1 , further comprising:
a source material and a drain material coupled at opposite ends of the channel material within a dimension substantially orthogonal to the first width, wherein:
the source material and the drain material each comprises an impurity and is epitaxial to the channel material; and
the source material and the drain material each has a lateral width larger than the first lateral width, and that is asymmetrical about a centerline of the first lateral width.

10 . The IC structure of claim 1 , wherein the channel material comprises:
a first channel material layer in a stack with a second channel material layer.

11 . An integrated circuit (IC) device, comprising:
a first transistor structure comprising:
a first channel material having a first lateral width in a first dimension; and
a first portion gate material over, and adjacent to the channel material, wherein the first portion of gate material extends a first height in a second dimension orthogonal to a reference plane;
a first gate mask structure over the first portion of the gate material, wherein the first gate mask structure and has a second lateral width in the first dimension, the second lateral width larger than the first lateral width; a second transistor structure laterally adjacent to a first side of the first transistor structure, the second transistor structure comprising:
a second channel material having the first lateral width in the first dimension; and
a second portion of the gate material over, and laterally adjacent to, the second channel material, wherein the second portion of the gate material extends the first height in the second dimension;
a second gate mask structure over the second portion of the gate material, wherein the second gate mask structure and has the second lateral width; and a third portion of the gate material laterally adjacent to a second side of the first transistor structure, opposite the second transistor structure, the third portion of the gate material extending a second height in the second dimension, the second height greater than the first height by more than 10 nm.

12 . The IC device of claim 11 , wherein a top surface of the third portion of the gate material is substantially coplanar with a top surface of at least the first gate mask structures.

13 . The IC structure of claim 11 , wherein the IC structure further comprises an electrical routing feature comprising the third portion of the gate material.

14 . The IC device of claim 11 , further comprising an insulator material or an air gap bifurcating the first portion of the gate material from the second portion of the gate material.

15 . The IC device of claim 14 , further comprising the insulator material or a second air gap bifurcating the third portion of the gate material from the first portion of the gate material.

16 . A method, comprising:
patterning a first mask material over a transistor channel material, the first mask material of a first width in a first dimension; forming a gate material adjacent to a sidewall of the transistor channel material and adjacent to a sidewall of the first mask material; selectively forming a second mask material over the gate material, and adjacent to the first mask material; exposing a sidewall of the gate material by thinning the first mask material; recessing the sidewall of the gate material to define an opening of a second width in the first dimension, larger than the first width; depositing a third mask material into the opening; and removing a portion of the gate material unprotected by the third mask material.

17 . The method of claim 16 , wherein:
the first mask material comprises at least a top material layer over a bottom material layer, the bottom material layer proximal to the transistor channel material; thinning the first mask material comprises removing the top material while retaining the bottom material layer; and the bottom material layer protects an underlying portion of the gate material while recessing the sidewall of the gate material.

18 . The method of claim 16 , wherein selectively forming the second mask material comprises selectively depositing amorphous silicon directly on a surface of the gate material.

19 . The method of claim 16 , wherein:
patterning the first mask material defines first lines extending in a second direction, orthogonal to the first dimension; and removing the portion of the gate material comprises etching a trench through a portion of the gate material between the third mask material and a planar substrate surface below the transistor channel material.

20 . The method of claim 19 , further comprising defining etch mask lines over the third mask material, the etch mask lines substantially parallel to the first lines, and etching the trench within a space between adjacent ones of the etch mask lines.

Assignees

• Intel Corp

Inventors

• Koh Shao-Ming
• Chandhok Manish
• Paik Marvin
• Haque Shahidul
• Klaus Jason
• Iqbal Asad
• Morrow Patrick
• Mehta Nikhil
• Davis Alison
• Pursel Sean
• Shen Steven
• Rochester Christopher
• Prince Matthew

Classifications

• H10P50/267 Primary

  using plasmas · CPC title

• H10P50/71

  using masks for conductive or resistive materials · CPC title

• H10D64/01326

  Aspects related to lithography, isolation or planarisation of the conductor · CPC title

• H10D84/0153

  using gate cut processes · CPC title

• H10D30/019

  of FETs having stacked nanowire, nanosheet or nanoribbon channels · CPC title