Synthesizing composite signals

Patent metadata

Field	Value
Publication number	US-2024421847-A1
Application number	US-202418743689-A
Country	US
Kind code	A1
Filing date	Jun 14, 2024
Priority date	Jun 14, 2023
Publication date	Dec 19, 2024
Grant date	—

Abstract

A technique for generating electronic signals includes processing a respective first-level input signal by each of a plurality of first-level channels, including up-sampling the respective first-level input signal and single-sideband (SSB) modulating the up-sampled first-level input signal to produce a respective first-level output signal. The technique further includes processing a respective second-level input signal by each of a plurality of second-level channels, including up-sampling the respective second-level input signal and SSB-modulating the up-sampled second-level input signal to produce a respective second-level output signal. The plurality of second-level channels is arranged in multiple groups assigned to respective first-level channels, and the technique further includes (i) summing together the second-level output signals of the second-level channels in each group, (ii) providing a group sum as the first-level input signal to the first-level channel to which the group is assigned, and summing together the first-level output signals to provide a composite signal.

First claim

What is claimed is:

1 . A synthesizer for generating electronic signals, comprising:
a plurality of first-level channels, each of the plurality of first-level channels constructed and arranged to up-sample and single-sideband (SSB) modulate a respective first-level input signal to produce a respective first-level output signal; a plurality of second-level channels, each of the plurality of second-level channels constructed and arranged to up-sample and SSB-modulate a respective second-level input signal to produce a respective second-level output signal, the plurality of second-level channels arranged in multiple groups wherein each group is provided for a respective first-level channel and includes multiple second-level channels whose second-level output signals combine to provide the first-level input signal of the respective first-level channel; and a summer constructed and arranged to sum together the first-level output signals to produce a composite output signal.

2 . The synthesizer of claim 1 , wherein the composite output signal has a first bandwidth range, wherein the first-level input signal of each first-level channel has a second bandwidth range that is narrower than the first bandwidth range, and wherein each first-level channel is further constructed and arranged to place the respective first-level input signal within a respective subrange of the first bandwidth range of the composite signal.

3 . The synthesizer of claim 2 , wherein each second-level channel in a group is constructed and arranged to receive a second-level input signal having a third bandwidth range that is narrower than the second bandwidth range, and wherein each second-level channel in the group is further constructed and arranged to place the respective second-level input signal within a respective subrange of the second bandwidth range.

4 . The synthesizer of claim 1 , wherein each of the plurality of first-level channels includes:
an up-sampler configured to multiply a sampling rate of the respective first-level input signal to produce a respective up-sampled first-level input signal; an oscillator that includes (i) an address sequencer configured to cycle through a sequence of stored values and (ii) a set of lookup tables that associates the stored values with respective sinusoidal values; and an SSB modulator having inputs configured to receive the up-sampled first-level input signal and the sinusoidal values and an output configured to produce the respective first-level output signal.

5 . The synthesizer of claim 1 , wherein each of the plurality of first-level channels and each of the plurality of second-level channels respectively includes an oscillator that includes (i) an address sequencer configured to cycle through a sequence of stored values and (ii) a set of lookup tables that associates the stored values with respective sinusoidal values.

6 . The synthesizer of claim 5 , wherein the stored values correspond to phase, and wherein the address sequencer is constructed and arranged to output the values at a consistent clock rate.

7 . The synthesizer of claim 6 , wherein the address sequencer is constructed and arranged to output a value at a first address after outputting a value from a last address, such that the address sequencer operates in a continuous loop.

8 . The synthesizer of claim 7 , wherein the oscillator is programmable for producing different frequencies of sinusoids by storing different numbers of 360-degree phase cycles in the stored values.

9 . The synthesizer of claim 5 , further comprising an input circuit constructed and arranged to produce the second-level input signal of a second-level channel of the plurality of second-level channels, the input circuit including a direct digital synthesizer (DDS) constructed and arranged to generate a sub-carrier frequency having a frequency resolution, wherein a component of the composite output signal contributed by the second-level channel has the same frequency resolution as the sub-carrier frequency produced by the DDS.

10 . The synthesizer of claim 1 , further comprising:
an up-sampler constructed and arranged to receive the composite output signal and to multiply a sampling rate of the composite output signal to provide an upsampled composite signal; a carrier DDS constructed and arranged to modulate the up-sampled composite signal on a carrier frequency; and a digital-to-analog converter constructed and arranged to convert the modulated, up-sampled composite signal to an analog signal.

11 . The synthesizer of claim 10 , wherein the modulator includes a local oscillator constructed and arranged to generate the carrier signal, the local oscillator including (i) an address sequencer configured to cycle through a sequence of stored values and (ii) a set of lookup tables that associates the stored values with respective sinusoidal values.

12 . The synthesizer of claim 1 , further comprising an input circuit constructed and arranged to produce the second-level input signal of a second-level channel of the plurality of second-level channels, the input circuit including:
a direct digital synthesizer (DDS) constructed and arranged to generate a sub-carrier frequency; a digital fine delay (DFD) circuit having an input coupled to a signal source for receiving an input signal having a sampling period; and an SSB modulator having a first input coupled to the DFD circuit, a second input coupled to the DDS, and an output coupled to the second-level channel for providing the second-level input signal, wherein the DFD circuit is constructed and arranged to selectively delay the input signal by time increments that are less than one percent of the sampling period of the input signal.

13 . The synthesizer of claim 1 , further comprising a digital fine delay (DFD) circuit having an input coupled to a signal source for receiving an input signal and an output coupled to one of the second-level channels for providing a delayed signal, wherein the DFD circuit includes:
a FIFO (first-in, first out buffer), the FIFO having an input configured to receive successive samples of the input signal and an output configured to provide delayed versions of the successive samples; a unit-delay circuit having an input and an output, the input of the unit-delay circuit coupled to the output of the FIFO; and a linear time interpolator having a first input coupled to the output of the FIFO, a second input coupled to the output of the unit-delay circuit, a third input providing a control signal for selecting a desired delay, and an output configured to provide the delayed signal delayed by an amount of time based on the control signal.

14 . The synthesizer of claim 13 , wherein the input signal provided to the input of the DFD circuit has a spectral fill that does not exceed 16%.

15 . The synthesizer of claim 1 , further comprising a digital fine delay (DFD) circuit having an input coupled to a signal source for receiving an input signal and an output coupled to one of the first-level channels for providing a delayed signal, the input signal having a spectral fill between 16% and 32%, wherein the DFD circuit includes:
a FIFO (first-in, first out buffer), the FIFO having an input configured to receive successive samples of the input signal and an output configured to provide delayed versions of the successive samples; a first unit-delay circuit having an input and an output, the input of the unit-delay circuit coupled to the output of the FIFO; a second unit-delay circuit having an input and an output, the input of the second unit-delay circuit coupled to the o

Assignees

• Textron Systems Corp

Inventors

• Jaklitsch James Joseph
• Markey Jay Michael

Classifications

• H04L27/04

  Modulator circuits; Transmitter circuits · CPC title

• H03C1/60

  with one sideband wholly or partially suppressed · CPC title

• H04L27/24

  Half-wave signalling systems · CPC title

• H04B14/002

  characterised by the use of a carrier modulation (using subcarrier modulation H04B14/08) · CPC title

• H04B1/0003

  Software-defined radio [SDR] systems, i.e. systems wherein components typically implemented in hardware, e.g. filters or modulators/demodulators, are implented using software, e.g. by involving an AD or DA conversion stage such that at least part of the signal processing is performed in the digital domain (digital baseband systems H04L25/00; digital modulation/demodulation H04L27/00; CDMA H04B1/707; TDMA H04B7/2643; image transmission H04N5/00) · CPC title