Methods and Circuitry for Reducing Mixer Harmonics Conversion Gain and Local Oscillator Fundamental and Harmonics Feedthrough

Patent metadata

Field	Value
Publication number	US-2024421769-A1
Application number	US-202318336786-A
Country	US
Kind code	A1
Filing date	Jun 16, 2023
Priority date	Jun 16, 2023
Publication date	Dec 19, 2024
Grant date	—

Abstract

Mixer circuitry can include a first pair of transistors coupled to a first tail node and configured to receive a local oscillator signal, a second pair of transistors coupled to a second tail node and configured to receive the local oscillator signal, a first digital-to-analog converter, a second DAC coupled between the first DAC and of the first pair of transistors, and a third DAC coupled between the first DAC and the second pair of transistors. During a first phase, control circuitry can sweep the first DAC to trim a first and/or other odd order local oscillator feedthrough. During a second phase, the control circuitry can sweep the second DAC to trim a second and/or other even order local oscillator feedthrough. During a third phase, the control circuitry can sweep the second and third DACs to reject signals associated with a second harmonic conversion gain of the mixer circuitry.

First claim

What is claimed is:

1 . Mixer circuitry comprising:
a first mixer transistor configured to receive a first oscillating signal and coupled to a first tail node; a second mixer transistor configured to receive a second oscillating signal and coupled to the first tail node; a first digital-to-analog converter (DAC); and a second digital-to-analog converter (DAC) coupled between the first DAC and the first mixer transistor.

2 . The mixer circuitry of claim 1 , wherein the second DAC comprises:
a first output coupled to a gate terminal of the first mixer transistor; and a second output coupled to a gate terminal of the second mixer transistor.

3 . The mixer circuitry of claim 2 , further comprising:
a first resistor coupled between the first output of the second DAC and the gate terminal of the first mixer transistor; and a second resistor coupled between the second output of the second DAC and the gate terminal of the second mixer transistor.

4 . The mixer circuitry of claim 1 , further comprising:
a third mixer transistor configured to receive the first oscillating signal and coupled to a second tail node; a fourth mixer transistor configured to receive the second oscillating signal and coupled to the second tail node; and a third digital-to-analog converter (DAC) coupled between the first DAC and the third mixer transistor.

5 . The mixer circuitry of claim 4 , wherein the first DAC comprises:
a first output coupled to the second DAC; and a second output coupled to the third DAC.

6 . The mixer circuitry of claim 4 , wherein the third DAC comprises:
a first output coupled to a gate terminal of the third mixer transistor; and a second output coupled to a gate terminal of the fourth mixer transistor.

7 . The mixer circuitry of claim 6 , further comprising:
a first resistor coupled between the first output of the third DAC and the gate terminal of the third mixer transistor; and a second resistor coupled between the second output of the third DAC and the gate terminal of the fourth mixer transistor.

8 . The mixer circuitry of claim 4 , further comprising:
a transformer coupled to the first and second tail nodes.

9 . The mixer circuitry of claim 4 , wherein:
the first mixer transistor has a drain terminal coupled to a first mixer output; the second mixer transistor has a drain terminal coupled to a second mixer output; the third mixer transistor has a drain terminal coupled to the first mixer output; and the fourth mixer transistor has a drain terminal coupled to the second mixer output.

10 . The mixer circuitry of claim 4 , further comprising control circuitry configured to:
trim the first DAC during a first calibration phase; trim the second DAC during a second calibration phase subsequent to the first calibration phase; and trim the second and third DACs during a third calibration phase subsequent to the second calibration phase.

11 . Mixer circuitry comprising:
a first pair of transistors coupled to a first tail node and having first gate terminals configured to receive a local oscillator signal; a second pair of transistors coupled to a second tail node and having second gate terminals configured to receive the local oscillator signal; a first digital-to-analog converter (DAC); a second digital-to-analog converter (DAC) coupled between the first DAC and the first gate terminals of the first pair of transistors; and a third digital-to-analog converter (DAC) coupled between the first DAC and the second gate terminals of the second pair of transistors.

12 . The mixer circuitry of claim 11 , further comprising:
a coil having a first terminal coupled to the first tail node and having a second terminal coupled to the second tail node.

13 . The mixer circuitry of claim 11 , wherein the first DAC comprises:
a first output coupled to the second DAC; and a second output coupled to the third DAC.

14 . The mixer circuitry of claim 11 , further comprising control circuitry configured to:
tune the first DAC during a first calibration phase; tune the second DAC during a second calibration phase subsequent to the first calibration phase; and tune the second and third DACs during a third calibration phase subsequent to the second calibration phase.

15 . The mixer circuitry of claim 11 , further comprising control circuitry configured to:
trim a direct current (DC) mismatch between the first tail node and the second tail node by adjusting the first DAC; trim an impedance at the first tail node by adjusting the second DAC; and trim a DC level of the local oscillator signal by adjusting the second DAC together with the third DAC.

16 . A method of operating mixer circuitry, comprising:
receiving a first oscillating signal at a gate terminal of a first mixer transistor; receiving a second oscillating signal at a gate terminal of a second mixer transistor, the first and second mixer transistors coupled to a first tail node; and with a second digital-to-analog converter (DAC), receiving a bias voltage from a first digital-to-analog converter (DAC), outputting a first bias voltage to the gate terminal of the first mixer transistor, and outputting a second bias voltage to the gate terminal of the second mixer transistor.

17 . The method of claim 16 , further comprising:
receiving the first oscillating signal at a gate terminal of a third mixer transistor; receiving the second oscillating signal at a gate terminal of a fourth mixer transistor, the third and fourth mixer transistors coupled to a second tail node; and with a third digital-to-analog converter (DAC), receiving another bias voltage from the first digital-to-analog converter (DAC), outputting a third bias voltage to the gate terminal of the third mixer transistor, and outputting a fourth bias voltage to the gate terminal of the fourth mixer transistor.

18 . The method of claim 17 , further comprising:
during a first phase, trimming an offset of the first DAC; during a second phase different than the first phase, trimming an offset of the second DAC with respect to an offset of the third DAC; and during a third phase different than the second phase, trimming the offset of the second DAC together with the offset of the third DAC.

19 . The method of claim 17 , further comprising:
during a first phase, trimming a direct current (DC) mismatch between the first tail node and the second tail node; during a second phase different than the first phase, trimming an impedance at the first tail node with respect to an impedance at the second tail node; and during a third phase different than the second phase, trimming a DC level of the first oscillating signal with respect to a DC level of the second oscillating signal.

20 . The method of claim 17 , further comprising:
during a first phase, sweeping the first DAC to trim a first order local oscillator feedthrough; during a second phase different than the first phase, sweeping the second DAC to trim a second order local oscillator feedthrough; and during a third phase different than the second phase, sweeping the second and third DACs to reject signals associated with a second harmonic gain of the mixer circuitry.

Assignees

• Apple Inc

Inventors

• Elaasar Omar E
• He Shan
• Zhang Gang
• Chakrabarti Anandaroop

Classifications

• H03D7/1441 Primary

  using field-effect transistors (H03D7/145 takes precedence) · CPC title

• H03M1/66

  Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H03M1/685

  the quantisation value generators of both converters being arranged in a common two-dimensional array · CPC title

• H03D7/1491

  Arrangements to linearise a transconductance stage of a mixer arrangement · CPC title

• H03D2200/0052

  Digital to analog conversion · CPC title