Semiconductor device

Patent metadata

Field	Value
Publication number	US-2024421232-A1
Application number	US-202418586125-A
Country	US
Kind code	A1
Filing date	Feb 23, 2024
Priority date	Jun 15, 2023
Publication date	Dec 19, 2024
Grant date	—

Abstract

A semiconductor device includes a lower pattern extending in a first direction, a plurality of wire patterns spaced apart from the lower pattern in a second direction on the lower pattern, and a gate electrode surrounding the plurality of wire patterns and extending in a third direction, on the lower pattern. Each of the plurality of wire patterns includes a transition metal dichalcogenide (TMD) material. Each of the plurality of wire patterns includes a pair of first areas protruding from sidewalls of the gate electrode in the first direction and a second area between the first areas. A phase of the first area is different from a phase of the second area.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a lower pattern extending in a first direction; a plurality of wire patterns disposed on the lower pattern and spaced apart from the lower pattern in a second direction; and a gate electrode surrounding the plurality of wire patterns, disposed on the lower pattern, and extending in a third direction, wherein each of the plurality of wire patterns includes a transition metal dichalcogenide (TMD) material, wherein each of the plurality of wire patterns includes:
a pair of first areas protruding from sidewalls of the gate electrode in the first direction, and
a second area between the first areas, and
wherein a phase of each first area of the pair is different from a phase of the second area.

2 . The semiconductor device of claim 1 , further comprising:
a source/drain pattern disposed on the sidewalls of the gate electrode and connected to the plurality of wire patterns, wherein the source/drain pattern includes a semimetal material.

3 . The semiconductor device of claim 2 , wherein the source/drain pattern surrounds the pair of first areas.

4 . The semiconductor device of claim 2 , wherein the source/drain pattern has a single layer.

5 . The semiconductor device of claim 1 , wherein a thickness of each of the plurality of wire patterns in the second direction is 1 nm or less.

6 . The semiconductor device of claim 1 , wherein a molecular structure of the pair of first areas has a first angle between i) a first connection between a transition metal and a first chalcogen element and ii) a second connection between the transition metal and a second chalcogen element adjacent to the first chalcogen element in a plan view of the molecular structure of the pair of first areas,
wherein a molecular structure of the second area has a second angle between iii) a third connection between the transition metal and a third chalcogen element and ii) a fourth connection between the transition metal and a fourth chalcogen element adjacent to the third chalcogen element in a plan view of the molecular structure of the second area, and wherein the first angle is less than the second angle.

7 . The semiconductor device of claim 1 , wherein in a molecular structure of the pair of first areas, six chalcogen elements are disposed around one transition metal in a plan view of the molecular structure of the pair of first areas, and
wherein in a molecular structure of the second area, three chalcogen elements are disposed around one transition metal in a plan view of the molecular structure of the second area.

8 . The semiconductor device of claim 1 , further comprising:
a barrier pattern surrounding the pair of first areas, wherein a transition metal included in the barrier pattern is a Group 4 transition metal.

9 . A semiconductor device comprising:
a lower pattern extending in a first direction; a plurality of wire patterns disposed on the lower pattern and spaced apart from the lower pattern in a second direction; a plurality of gate electrodes surrounding the plurality of wire patterns, disposed on the lower pattern, extending in a third direction, and spaced apart from each other in the first direction; and a source/drain pattern connected to the plurality of wire patterns between the plurality of gate electrodes, wherein each of the plurality of wire patterns includes a transition metal dichalcogenide (TMD) material, wherein each of the plurality of wire patterns includes:
a first area surrounded by the source/drain pattern, and
a second area that is not in contact with the source/drain pattern,
wherein a molecular structure of the first area has a first angle between i) a first connection between a transition metal and a first chalcogen element and ii) a second connection between the transition metal and a second chalcogen element adjacent to the first chalcogen element in a plan view of the molecular structure of the pair of first areas, wherein a molecular structure of the second area has a second angle between iii) a third connection between the transition metal and a third chalcogen element and ii) a fourth connection between the transition metal and a fourth chalcogen element adjacent to the third chalcogen element in a plan view of the molecular structure of the second area, and wherein the first angle is less than the second angle.

10 . The semiconductor device of claim 9 , wherein the source/drain pattern includes a semimetal material.

11 . The semiconductor device of claim 9 , wherein in the molecular structure of the first area, six chalcogen elements are disposed around one transition metal a plan view of the molecular structure of the pair of first areas, and
wherein in the molecular structure of the second area, three chalcogen elements are disposed around one transition metal in a plan view of the molecular structure of the second area.

12 . The semiconductor device of claim 9 , wherein a phase of the first area is different from a phase of the second area.

13 . The semiconductor device of claim 9 , wherein a thickness of each of the plurality of wire patterns in the second direction is 1 nm or less.

14 . The semiconductor device of claim 9 , wherein the source/drain pattern has a single layer.

15 . The semiconductor device of claim 9 , further comprising:
a barrier pattern disposed between the first area and the source/drain pattern, wherein a transition metal included in the barrier pattern includes a Group 4 transition metal.

16 . A semiconductor device comprising:
a lower pattern extending in a first direction; a plurality of wire patterns disposed on the lower pattern and spaced apart from the lower pattern in a second direction, wherein each wire pattern of the plurality of wire patterns includes a pair of first areas spaced apart from each other in the first direction and a second area between the pair of first areas; a plurality of gate electrodes surrounding second areas of the plurality of wire patterns, disposed on the lower pattern, extending in a third direction, and spaced apart from each other in the first direction; a source/drain pattern connected to the plurality of wire patterns between the plurality of gate electrodes that are adjacent to each other; and a barrier pattern interposed between the pair of first areas and the source/drain pattern, wherein each of the plurality of wire patterns includes a transition metal dichalcogenide (TMD) material, and wherein a transition metal included in the barrier pattern is a Group 4 transition metal.

17 . The semiconductor device of claim 16 , wherein the source/drain pattern includes a semimetal material.

18 . The semiconductor device of claim 16 , wherein a thickness of each of the plurality of wire patterns in the second direction is 1 nm or less.

19 . The semiconductor device of claim 16 , wherein a molecular structure of the pair of first areas has a first angle between i) a first connection between a transition metal and a first chalcogen element and ii) a second connection between the transition metal and a second chalcogen element adjacent to the first chalcogen element in a plan view of the molecular structure of the pair of first areas,
wherein a molecular structure of the second area has a second angle between iii) a third connection between the transition metal and a third chalcogen element and ii) a fourth connection between the transition metal and a fourth chalcogen element adjacent to the third chalcogen element in a pla

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yang suk
• Jang Sung-Hwan
• Kim Do Hee
• Kim Jin Bum
• Jang Sung Uk
• Zoh Inhae

Classifications

• H10D30/6757 Primary

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D30/502

  characterised by the stacked channels · CPC title

• H10D64/512

  Disposition of the gate electrodes, e.g. buried gates · CPC title

• H10D62/121

  oriented parallel to substrates · CPC title