Integrated circuit device

Patent metadata

Field	Value
Publication number	US-2024421162-A1
Application number	US-202318529716-A
Country	US
Kind code	A1
Filing date	Dec 5, 2023
Priority date	Jun 14, 2023
Publication date	Dec 19, 2024
Grant date	—

Abstract

An integrated circuit device includes a backside insulating structure including an etch stop pattern, gate lines arranged over the backside insulating structure and each overlapping the etch stop pattern in a vertical direction, source/drain regions respectively arranged one-by-one between the gate lines, and a backside via contact passing through the etch stop pattern in the vertical direction and connected to a first source/drain region selected from the source/drain regions, wherein the backside via contact includes a stepped portion, which is apart from a first vertical level in the vertical direction by as much as a first distance and has a change in the width of the backside via contact in a horizontal direction at a second vertical level that is adjacent to the etch stop pattern, the first vertical level being closest to the plurality of gate lines in the backside insulating structure.

First claim

What is claimed is:

1 . An integrated circuit device comprising:
a backside insulating structure comprising an etch stop pattern; a plurality of gate lines over the backside insulating structure and each at least partly overlapping the etch stop pattern in a vertical direction; a plurality of source/drain regions respectively arranged one-by-one between the plurality of gate lines; and a backside via contact passing through the etch stop pattern in the vertical direction and connected to a first source/drain region selected from the plurality of source/drain regions, wherein the backside via contact comprises a stepped portion apart from a first vertical level in the vertical direction by as much as a first distance and having a change in width in a horizontal direction at a second vertical level that is adjacent to the etch stop pattern, the first vertical level being closest to the plurality of gate lines in the backside insulating structure.

2 . The integrated circuit device of claim 1 , further comprising:
a place holder at least partly overlapping a second source/drain region in the vertical direction, the second source/drain region selected from the plurality of source/drain regions and apart from the first source/drain region in the horizontal direction, wherein the place holder comprises a holder upper surface contacting the second source/drain region, a holder sidewall facing the backside via contact in the horizontal direction with a portion of the backside insulating structure therebetween, and a holder lower surface that is opposite to the holder upper surface in the vertical direction, and the holder sidewall and the holder lower surface of the place holder are in contact with the backside insulating structure.

3 . The integrated circuit device of claim 2 , wherein the backside insulating structure further comprises an inner backside insulating pattern between the etch stop pattern and the plurality of gate lines and comprising a different material from any constituent material of the etch stop pattern,
the holder sidewall of the place holder is in contact with the inner backside insulating pattern, and the holder lower surface of the place holder is in contact with the etch stop pattern.

4 . The integrated circuit device of claim 2 , wherein
the backside insulating structure further comprises an inner backside insulating pattern between the etch stop pattern and the plurality of gate lines and comprising a different material from any constituent material of the etch stop pattern, the etch stop pattern comprises a first liner portion, which is in contact with the inner backside insulating pattern, and a second liner portion, which is in contact with the holder lower surface of the place holder, and the second liner portion of the etch stop pattern has a cross-sectional shape that is concave toward the place holder.

5 . The integrated circuit device of claim 2 , wherein
The backside insulating structure further comprises an outer backside insulating pattern apart from the plurality of gate lines in the vertical direction with the etch stop pattern therebetween and comprises a different material from any constituent material of the etch stop pattern, the etch stop pattern comprises a gap-fill pattern, which fills a space between the backside via contact and the place holder, the holder sidewall of the place holder is in contact with the etch stop pattern, and the holder lower surface of the place holder is in contact with the outer backside insulating pattern.

6 . The integrated circuit device of claim 2 , wherein
the backside insulating structure further comprises an outer backside insulating pattern apart from the plurality of gate lines in the vertical direction with the etch stop pattern therebetween and comprises a different material from any constituent material of the etch stop pattern, and the outer backside insulating pattern has a surface that is concave toward the holder lower surface of the place holder.

7 . The integrated circuit device of claim 1 , wherein the backside insulating structure further comprises:
an inner backside insulating pattern between the etch stop pattern and the plurality of gate lines; and an outer backside insulating pattern, which is apart from the inner backside insulating pattern in the vertical direction with the etch stop pattern therebetween, each of the inner backside insulating pattern and the outer backside insulating pattern comprises a different material from any constituent material of the etch stop pattern, the etch stop pattern comprises a portion extending flat in the horizontal direction around the stepped portion of the backside via contact, and a thickness of the etch stop pattern in the vertical direction is less than a thickness of each of the inner backside insulating pattern and the outer backside insulating pattern in the vertical direction.

8 . The integrated circuit device of claim 7 , wherein
the backside via contact comprises a first contact portion passing through the inner backside insulating pattern, a second contact portion passing through the etch stop pattern, and a third contact portion passing through the outer backside insulating pattern, and, in the backside via contact, a sidewall of each of the first contact portion and the third contact portion is not in contact with the etch stop pattern.

9 . The integrated circuit device of claim 1 , wherein
the backside insulating structure further comprises an outer backside insulating pattern apart from the plurality of gate lines in the vertical direction with the etch stop pattern therebetween and is in contact with the etch stop pattern, the outer backside insulating pattern comprising a different material from any constituent materials of the etch stop pattern, and an interface between the etch stop pattern and the outer backside insulating pattern comprises a portion extending flat in the horizontal direction around the stepped portion of the backside via contact.

10 . The integrated circuit device of claim 9 , wherein
the backside via contact comprises a first contact portion, which passes through the etch stop pattern, and a second contact portion, which passes through the outer backside insulating pattern, and, in the backside via contact, a sidewall of the second contact portion is not in contact with the etch stop pattern.

11 . The integrated circuit device of claim 1 , further comprising:
a place holder apart from the backside via contact in the horizontal direction, wherein the place holder is in contact with the etch stop pattern and a second source/drain region, which is selected from the plurality of source/drain regions and is apart from the first source/drain region in the horizontal direction, the place holder comprises a first film, which is selected from a doped SiGe film, an undoped SiGe film, an aluminum oxide film, a titanium oxide film, a silicon nitride film, and a combination thereof, and the etch stop pattern comprises a second film, which is selected from an aluminum oxide film, a titanium oxide film, a silicon nitride film, and a combination thereof, the second film comprising a different material from any constituent material of the first film.

12 . The integrated circuit device of claim 1 , wherein
the backside insulating structure further comprises an inner backside insulating pattern arranged between the etch stop pattern and the plurality of gate lines and comprises a different material from any constituent material of the etch stop pattern, the backside via contact comprises a first contact portion, which has a sidewall contacting the inner backs

Assignees

• Samsung Electronics Co Ltd

Inventors

• Ahn Minchul
• Kim Yeonggil
• Park Sungbin
• Jung Deokyoung

Classifications

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10D64/254

  for lateral devices wherein the source or drain electrodes extend entirely through the semiconductor bodies, e.g. via-holes for back side contacts · CPC title

• H10D84/832

  comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels · CPC title

• H10D84/0149

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title

• H10D84/013

  Manufacturing their source or drain regions, e.g. silicided source or drain regions · CPC title