Semiconductor devices and methods of fabricating the same

Patent metadata

Field	Value
Publication number	US-2024421070-A1
Application number	US-202418409491-A
Country	US
Kind code	A1
Filing date	Jan 10, 2024
Priority date	Jun 19, 2023
Publication date	Dec 19, 2024
Grant date	—

Abstract

Disclosed are semiconductor devices and their fabrication methods. The semiconductor device comprises a substrate including an active pattern; a channel pattern on the active pattern; a source/drain pattern electrically connected to the channel pattern; a gate electrode on the channel pattern; an interlayer dielectric layer on the gate electrode, wherein the interlayer dielectric layer includes a recess; a via in the recess; a wiring line on the interlayer dielectric layer and electrically connected to the via; and an adhesion layer between the wiring line and an upper surface of the interlayer dielectric layer, wherein an upper surface of the via is closer than the upper surface of the interlayer dielectric layer to the substrate in a first direction, wherein the first direction is perpendicular to an upper surface of the substrate and wherein a portion of the adhesion layer is on a portion of an inner sidewall of the recess.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a substrate that includes an active pattern; a channel pattern on the active pattern; a source/drain pattern electrically connected to the channel pattern; a gate electrode on the channel pattern; an interlayer dielectric layer on the gate electrode, wherein the interlayer dielectric layer includes a recess; a via in the recess of the interlayer dielectric layer; a wiring line on the interlayer dielectric layer and electrically connected to the via; and an adhesion layer between the wiring line and an upper surface of the interlayer dielectric layer, wherein an upper surface of the via is closer than the upper surface of the interlayer dielectric layer to the substrate in a first direction, wherein the first direction is perpendicular to an upper surface of the substrate and wherein a portion of the adhesion layer is on a portion of an inner sidewall of the recess.

2 . The semiconductor device of claim 1 , wherein the wiring line includes a line portion and a protrusion portion that extends from the line portion in the first direction,
wherein the line portion is on the upper surface of the interlayer dielectric layer, and wherein at least a portion of the protrusion portion is in the recess of the interlayer dielectric layer.

3 . The semiconductor device of claim 2 , wherein the protrusion portion of the wiring line is in contact with the upper surface of the via.

4 . The semiconductor device of claim 1 , wherein the upper surface of the via has a shape that is convex toward the wiring line.

5 . The semiconductor device of claim 1 , wherein at least a portion of the upper surface of the via is exposed through the adhesion layer to be in contact with the wiring line.

6 . The semiconductor device of claim 1 , wherein the adhesion layer has a sidewall aligned with one sidewall of the wiring line.

7 . The semiconductor device of claim 1 , wherein the via is electrically connected to the source/drain pattern or the gate electrode.

8 . The semiconductor device of claim 1 , wherein the wiring line includes ruthenium (Ru).

9 . The semiconductor device of claim 1 , further comprising a contact between the source/drain pattern and the via or between the gate electrode and the via,
wherein the contact includes:
a conductive pattern; and
a barrier pattern on sidewalls and a lower surface of the conductive pattern.

10 . The semiconductor device of claim 1 , wherein the channel pattern includes a plurality of semiconductor patterns that are spaced apart from each other and are stacked in the first direction,
wherein the gate electrode includes:
a plurality of inner electrodes between adjacent ones of the plurality of semiconductor patterns; and
an outer electrode on an uppermost one of the plurality of semiconductor patterns.

11 . A semiconductor device, comprising:
a substrate that includes an active pattern; a device isolation layer adjacent to the active pattern; a channel pattern on the active pattern, wherein the channel pattern includes a plurality of semiconductor patterns that are stacked and spaced apart from each other in a first direction, and wherein the first direction is perpendicular to an upper surface of the substrate; a source/drain pattern electrically connected to the plurality of semiconductor patterns; a gate electrode that extends around the plurality of semiconductor patterns; an active contact electrically connected to the source/drain pattern; a gate contact electrically connected to the gate electrode; an interlayer dielectric layer on the active contact and the gate contact, wherein the interlayer dielectric layer includes a recess; a via in the recess of the interlayer dielectric layer and electrically connected to the active contact or the gate contact; a plurality of wiring lines on the interlayer dielectric layer; and an adhesion layer between the interlayer dielectric layer and the plurality of wiring lines, wherein one of the plurality of wiring lines is electrically connected to the via, and wherein the adhesion layer extends from an upper surface of the interlayer dielectric layer to a portion of an inner sidewall of the recess.

12 . The semiconductor device of claim 11 , wherein an upper surface of the via is lower than the upper surface of the interlayer dielectric layer with respect to the upper surface of the substrate in the first direction.

13 . The semiconductor device of claim 11 , wherein each of the plurality of wiring lines includes a line portion and a protrusion portion that extends from the line portion in the first direction,
wherein the line portion is spaced apart from an upper surface of the via in the first direction.

14 . The semiconductor device of claim 13 , wherein the via and one of the plurality of wiring lines are integrally connected to each other.

15 . A method of fabricating a semiconductor device, the method comprising:
forming an interlayer dielectric layer on a substrate; patterning the interlayer dielectric layer to form a recess; forming a via in the recess; forming an adhesion layer that is on a portion of an inner sidewall of the recess and an upper surface of the interlayer dielectric layer, wherein the adhesion layer exposes an upper surface of the via; forming a wiring layer on the adhesion layer and the upper surface of the via; and patterning the wiring layer to form a plurality of wiring lines, wherein the upper surface of the via is lower than the upper surface of the interlayer dielectric layer with respect to an upper surface of the substrate in a first direction, and wherein the first direction is perpendicular to the upper surface of the substrate.

16 . The method of claim 15 , before forming the adhesion layer, the method further comprising forming a deposition prevention layer on the via.

17 . The method of claim 16 , wherein the deposition prevention layer includes octadecyl phosphonic acid (ODPA) and/or 1-hexadecanethiol.

18 . The method of claim 15 , wherein forming the via includes:
forming a conductive layer that is in the recess; and performing a planarization process on the conductive layer.

19 . The method of claim 15 , wherein forming the via includes using selective area growth.

20 . The method of claim 15 , wherein forming the plurality of wiring lines includes patterning the adhesion layer.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Sunjung
• Ahn Sanghoon
• Yoo Donggon
• Lee Jangeun
• Hwang Jeongwon

Classifications

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/081 Primary

  by forming openings in the dielectric parts · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/033

  in openings in dielectrics · CPC title

• H10W20/435 Primary

  Cross-sectional shapes or dispositions of interconnections · CPC title