Multilayer ceramic capacitor

Patent metadata

Field	Value
Publication number	US-2024420893-A1
Application number	US-202418805970-A
Country	US
Kind code	A1
Filing date	Aug 15, 2024
Priority date	Jun 13, 2023
Publication date	Dec 19, 2024
Grant date	—

Abstract

A multilayer ceramic capacitor includes a first extension portion, a first counter portion, a second extension portion, and a second counter portion. The first extension portion includes a first external electrode-side region, a first counter portion-side region, and a first intermediate region. The second extension portion includes a second external electrode-side region, a second counter portion-side region, and a second intermediate region. A coverage of the first intermediate region and the second intermediate region is lower than a coverage of the first external electrode-side region and the second external electrode-side region. The coverage of the first intermediate region and the second intermediate region is lower than a coverage of the first counter portion and the second counter portion.

First claim

What is claimed is:

1 . A multilayer ceramic capacitor comprising:
a multilayer body including a plurality of dielectric layers and a plurality of internal electrode layers that are laminated, a first main surface and a second main surface opposed to each other in a lamination direction, a first lateral surface and a second lateral surface opposed to each other in a width direction orthogonal or substantially orthogonal to the lamination direction, and a first end surface and a second end surface opposed to each other in a length direction orthogonal or substantially orthogonal to the lamination direction and the width direction; a first external electrode on the first end surface; and a second external electrode on the second end surface; wherein the plurality of internal electrode layers include first internal electrode layers and second internal electrode layers; the first internal electrode layers each include a first extension portion and a first counter portion, the first extension portion including one end portion that extends toward and is exposed at the first end surface and is connected to the first external electrode, the first counter portion being connected to the first extension portion and opposed to a corresponding one of the second internal electrode layers provided adjacent to each other in the lamination direction; the second internal electrode layers each include a second extension portion and a second counter portion, the second extension portion including one end portion that extends toward and is exposed at the second end surface and is connected to the second external electrode, the second counter portion being connected to the second extension portion and opposed to a corresponding one of the first internal electrode layers provided adjacent to each other in the lamination direction; the first extension portion includes a first external electrode-side region in a vicinity of a portion of the first extension portion connected with the first external electrode, a first counter portion-side region in a vicinity of a portion of the first extension portion connected with the first counter portions, and a first intermediate region located between the first external electrode-side region and the first counter portion-side region; the second extension portion includes a second external electrode-side region in a vicinity of a portion of the second extension portion connected with the second external electrode, a second counter portion-side region in a vicinity of a portion of the second extension portion connected with the second counter portions, and a second intermediate region located between the second external electrode-side region and the second counter portion-side region; a coverage of the first intermediate region and the second intermediate region is lower than a coverage of the first external electrode-side region and the second external electrode-side region; and the coverage of the first intermediate region and the second intermediate region is lower than a coverage of the first counter portion and the second counter portion.

2 . The multilayer ceramic capacitor according to claim 1 , wherein a coverage of the first counter portion-side region and the second counter portion-side region is higher than the coverage of the first intermediate region and the second intermediate region.

3 . The multilayer ceramic capacitor according to claim 1 , wherein the coverage of the first intermediate region and the second intermediate region is about 55% or more.

4 . The multilayer ceramic capacitor according to claim 1 , wherein the coverage of the first intermediate region and the second intermediate region is about 80% or less.

5 . The multilayer ceramic capacitor according to claim 1 , wherein the coverage of the first external electrode-side region and the second external electrode-side region is higher than the coverage of the first intermediate region and the second intermediate region, and is about 68% or more.

6 . The multilayer ceramic capacitor according to claim 1 , wherein the coverage of the first counter portion-side region and the second counter portion-side region is higher than the coverage of the first intermediate region and the second intermediate region, and is about 68% or more.

7 . The multilayer ceramic capacitor according to claim 1 , wherein the coverage of the first counter portion and the second counter portion is higher than the coverage of the first intermediate region and the second intermediate region, and is about 75% or more.

8 . The multilayer ceramic capacitor according to claim 1 , wherein a dimension in the length direction of the multilayer body is about 0.2 mm or more and about 6 mm or less, a dimension of the multilayer body in the lamination direction is about 0.05 mm or more and about 5 mm or less, and a dimension of the multilayer body in the width direction is about 0.1 mm or more and about 5 mm or less.

9 . The multilayer ceramic capacitor according to claim 1 , wherein the plurality of dielectric layers include BaTio 3 , CaTio 3 , SrTiO 3 , or CaZrO 3 .

10 . The multilayer ceramic capacitor according to claim 9 , wherein the plurality of dielectric layers further include a Mn compound, an Fe compound, a Cr compound, a Co compound, or a Ni compound.

11 . The multilayer ceramic capacitor according to claim 1 , wherein a thickness of each of the plurality of dielectric layers is about 0.2 μm or more and about 10 μm or less.

12 . The multilayer ceramic capacitor according to claim 1 , wherein the multilayer body includes fifteen or more and 1200 or less of the plurality of dielectric layers.

13 . The multilayer ceramic capacitor according to claim 1 , wherein the plurality of internal electrodes includes Ni, Cu, Ag, Pd or Au, or an alloy including at least one of Ni, Cu, Ag, Pd or Au.

14 . The multilayer ceramic capacitor according to claim 1 , wherein each of the plurality of internal electrodes has a thickness of about 0.2 μm or more and about 2.0 μm or less.

15 . The multilayer ceramic capacitor according to claim 1 , wherein each of the first external electrode and the second external electrode includes a base electrode layer and a plated electrode layer.

16 . The multilayer ceramic capacitor according to claim 15 , wherein each of the first external electrode and the second external electrode further includes an electrically conductive resin layer including electrically conductive particles and a resin.

17 . The multilayer ceramic capacitor according to claim 1 , wherein the first intermediate region has a length of about 60% or more and about 80% or less of the length in the length direction of the first extension portion; and
the second intermediate region has a length of about 60% or more and about 80% or less of the length in the length direction of the second extension portion.

18 . The multilayer ceramic capacitor according to claim 1 , wherein the coverage of the first external electrode-side region and the second external electrode-side region is higher than the coverage of the first intermediate region and the second intermediate region, and is about 88% or less.

19 . The multilayer ceramic capacitor according to claim 1 , wherein the coverage of the first counter portion-side region and the second counter portion-side region is higher than the coverage of the first intermediate region and the second intermediate region, and is about 88 or less.

Assignees

• Murata Manufacturing Co

Inventors

• Oguni Toshimi
• Yamada Mayumi
• Hirai Tomoaki
• Sugata Takeshi

Classifications

• H01G4/0085

  Fried electrodes · CPC title

• H01G4/12

  Ceramic dielectrics {(H01G4/085 takes precedence)} · CPC title

• H01G4/232

  electrically connecting two or more layers of a stacked or rolled capacitor · CPC title

• H01G4/2325

  characterised by the material of the terminals · CPC title

• H01G4/30

  Stacked capacitors (H01G4/33 takes precedence) · CPC title