Analog circuit and semiconductor device

Patent metadata

Field	Value
Publication number	US-2024413166-A1
Application number	US-202418805622-A
Country	US
Kind code	A1
Filing date	Aug 15, 2024
Priority date	Oct 21, 2009
Publication date	Dec 12, 2024
Grant date	—

Abstract

An object is to obtain a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range, using a thin film transistor in which an oxide semiconductor layer is used. An analog circuit is formed with the use of a thin film transistor including an oxide semiconductor which has a function as a channel formation layer, has a hydrogen concentration of 5×10 19 atoms/cm 3 or lower, and substantially functions as an insulator in the state where no electric field is generated. Thus, a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range can be obtained.

First claim

1 . (canceled)

2 . A semiconductor device comprising:
a first insulating layer; a first conductive layer over the first insulating layer; an oxide semiconductor layer comprising a channel formation region, a region in contact with a side surface of the first conductive layer, and a region in contact with a top surface of the first conductive layer; a second conductive layer comprising a region over the oxide semiconductor layer and a region configured to serve as a wiring layer; a second insulating layer over the oxide semiconductor layer; and a third conductive layer over the second insulating layer, wherein the first conductive layer is a single layer comprising molybdenum, wherein the oxide semiconductor layer comprises indium, gallium, and zinc, wherein the second conductive layer is a stacked layer comprising a first titanium film, a first aluminum film over the first titanium film, and a second titanium film over the first aluminum film, wherein the third conductive layer is a stacked layer comprising a third titanium film and a second aluminum film, wherein an end portion of the first conductive layer comprises a tapered shape, wherein the first insulating layer comprises a first region, a second region, and a third region between the first region and the second region, wherein the first region and the second region of the first insulating layer is in contact with a bottom surface of the oxide semiconductor layer, wherein the third region of the first insulating layer is in contact with a bottom surface of the first conductive layer, wherein the second conductive layer and the first conductive layer overlap each other, wherein the second conductive layer and the oxide semiconductor layer overlap each other, and wherein the second conductive layer and the second insulating layer overlap each other.

3 . The semiconductor device according to claim 2 , further comprising a third insulating layer over the second conductive layer.

4 . The semiconductor device according to claim 2 , wherein the oxide semiconductor layer comprises a microcrystalline portion.

5 . The semiconductor device according to claim 4 , wherein a grain diameter of the microcrystalline portion is greater than or equal to 1 nm and less than or equal to 20 nm.

6 . The semiconductor device according to claim 2 ,
wherein the first conductive layer is configured to serve as a source electrode or a drain electrode, wherein the second insulating layer is configured to serve as a gate insulating layer, and wherein the third conductive layer is configure to serve as a gate electrode.

7 . A semiconductor device comprising:
a first insulating layer; a first conductive layer over the first insulating layer; an oxide semiconductor layer comprising a channel formation region, a region in contact with a side surface of the first conductive layer, and a region in contact with a top surface of the first conductive layer; a second conductive layer comprising a region over the oxide semiconductor layer and a region configured to serve as a wiring layer; a second insulating layer over the oxide semiconductor layer; and a third conductive layer over the second insulating layer, wherein the first conductive layer is a single layer comprising molybdenum, wherein the oxide semiconductor layer comprises indium, gallium, and zinc, wherein the second conductive layer is a stacked layer comprising a first titanium film, a first aluminum film over the first titanium film, and a second titanium film over the first aluminum film, wherein the third conductive layer is a stacked layer comprising a third titanium film and a second aluminum film, wherein an end portion of the first conductive layer comprises a tapered shape, wherein the first insulating layer comprises a first region, a second region, and a third region between the first region and the second region in a cross-sectional view in a channel length direction, wherein the first region and the second region of the first insulating layer is in contact with a bottom surface of the oxide semiconductor layer, wherein the third region of the first insulating layer is in contact with a bottom surface of the first conductive layer, wherein the second conductive layer and the first conductive layer overlap each other, wherein the second conductive layer and the oxide semiconductor layer overlap each other, and wherein the second conductive layer and the second insulating layer overlap each other.

8 . The semiconductor device according to claim 7 , further comprising a third insulating layer over the second conductive layer.

9 . The semiconductor device according to claim 7 , wherein the oxide semiconductor layer comprises a microcrystalline portion.

10 . The semiconductor device according to claim 9 , wherein a grain diameter of the microcrystalline portion is greater than or equal to 1 nm and less than or equal to 20 nm.

11 . The semiconductor device according to claim 7 ,
wherein the first conductive layer is configured to serve as a source electrode or a drain electrode, wherein the second insulating layer is configured to serve as a gate insulating layer, and wherein the third conductive layer is configure to serve as a gate electrode.

12 . A semiconductor device comprising:
a first insulating layer; a first conductive layer over the first insulating layer; an oxide semiconductor layer comprising a channel formation region, a region in contact with a side surface of the first conductive layer, and a region in contact with a top surface of the first conductive layer; a second conductive layer comprising a region over the oxide semiconductor layer and a region configured to serve as a wiring layer; a second insulating layer over the oxide semiconductor layer; and a third conductive layer over the second insulating layer, wherein the first conductive layer is a single layer comprising molybdenum, wherein the oxide semiconductor layer comprises indium, wherein the second conductive layer is a stacked layer comprising a first titanium film, a first aluminum film over the first titanium film, and a second titanium film over the first aluminum film, wherein the third conductive layer is a stacked layer comprising a third titanium film and a second aluminum film, wherein an end portion of the first conductive layer comprises a tapered shape, wherein the first insulating layer comprises a first region, a second region, and a third region between the first region and the second region in a cross-sectional view in a channel length direction, wherein the first region and the second region of the first insulating layer is in contact with a bottom surface of the oxide semiconductor layer, wherein the third region of the first insulating layer is in contact with a bottom surface of the first conductive layer, wherein the second conductive layer and the first conductive layer overlap each other, wherein the second conductive layer and the oxide semiconductor layer overlap each other, and wherein the second conductive layer and the second insulating layer overlap each other.

13 . The semiconductor device according to claim 12 , further comprising a third insulating layer over the second conductive layer.

14 . The semiconductor device according to claim 12 , wherein the oxide semiconductor layer comprises a microcrystalline portion.

15 . The semiconductor device according to claim 14 , wherein a grain diameter of the microcrystalline portion is greater than or equal to 1 nm and less than or equal to 20 nm.

16 . The semico

Assignees

• Semiconductor Energy Lab

Inventors

• Yamazaki Shunpei
• Koyama Jun
• Hirose Atsushi
• Tsubuku Masashi
• Noda Kosei

Classifications

• G09G3/32

  semiconductive, e.g. using light-emitting diodes [LED] · CPC title

• H10D84/0128

  Manufacturing their channels · CPC title

• H10D62/10

  Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies · CPC title

• H10D30/6755

  Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate · CPC title

• H10D86/60 Primary

  wherein the TFTs are in active matrices · CPC title