Layout pattern for static random access memory

Patent metadata

Field	Value
Publication number	US-2024404587-A1
Application number	US-202318218025-A
Country	US
Kind code	A1
Filing date	Jul 4, 2023
Priority date	Jun 5, 2023
Publication date	Dec 5, 2024
Grant date	—

Abstract

The invention provides a layout pattern of static random access memory (SRAM), which comprises a substrate, and a plurality of fin structures and a plurality of gate structures are located on the substrate to form a plurality of transistors. The plurality of transistors comprise a first pull-up transistor (PU 1 ), a first pull-down transistor (PD 1 ), a second pull-up transistor (PU 2 ), a second pull-down transistor (PD 2 ), a first access transistor (PG 1 A), a second access transistor (PG 1 B), a third access transistor (PG 2 A) and a fourth access transistor (PG 2 B). A first word line contact pad connected to a gate of the first access transistor (PG 1 A) and a first word line, and a second word line contact pad connected to a gate of the second access transistor (PG 1 B) and a second word line, the first word line contact pad and the second word line contact pad do not overlap in a vertical direction.

First claim

What is claimed is:

1 . A layout pattern of a static random-access memory (SRAM), comprising:
a substrate; a plurality of fin structures are located on the substrate, and each fin structure extends along a second direction (Y direction); a plurality of gate structures are located on the substrate, and each gate structure extends along a first direction (X direction) and spans the plurality of fin structures to form a plurality of transistors, wherein the plurality of transistors comprise a first pull-up transistor (PU 1 ), a first pull-down transistor (PD 1 ), a second pull-up transistor (PU 2 ), a second pull-down transistor (PD 2 ), a first access transistor (PG 1 B), a first access transistor (PG 1 A), a second access transistor (PG 1 B), a third access transistor (PG 2 A) and a fourth access transistor (PG 2 B); a first word line contact pad connected to a gate of the first access transistor (PG 1 A) and a first word line; and a second word line contact pad connected to a gate of the second access transistor (PG 1 B) and a second word line, wherein the first word line contact pad and the second word line contact pad do not overlap in the second direction.

2 . The layout pattern of the SRAM according to claim 1 , wherein the layout pattern of the SRAM further comprising:
a first inverter including the first pull-up transistor (PU 1 ) and the first pull-down transistor (PD 1 ) located on the substrate; a second inverter including the second pull-up transistor (PU 2 ) and the second pull-down transistor (PD 2 ) located on the substrate, wherein the first inverter and the second inverter are coupled with each other.

3 . The layout pattern of the SRAM according to claim 2 , wherein the first access transistor (PG 1 A) and the second access transistor (PG 1 B) are connected to an output terminal of the first inverter, and the third access transistor (PG 2 A) and the fourth access transistor (PG 2 B) are connected to an output terminal of the second inverter.

4 . The layout pattern of the SRAM according to claim 1 , wherein one side of the first word line contact pad and one side of the second word line contact pad are aligned with each other in the second direction.

5 . The layout pattern of SRAM according to claim 1 , wherein the PG 1 A includes a first gate structure, the PG 1 B includes a second gate structure, the PG 2 A includes a third gate structure, the PG 2 B includes a fourth gate structure, the PU 2 and the PD 2 include a fifth gate structure, and the PU 1 and the PD 1 include a sixth gate structure.

6 . The layout pattern of the SRAM according to claim 5 , further comprising:
a third word line contact pad located on the third gate structure and connected to the first word line; and a fourth word line contact pad located on the fourth gate structure and connected to the second word line, wherein the third word line contact pad and the fourth word line contact pad do not overlap in the second direction.

7 . The layout pattern of the SRAM according to claim 5 , further comprising a first dummy gate structure located between the first gate structure and the fifth gate structure and aligned with the first gate structure and the fifth gate structure in the first direction.

8 . The layout pattern of the SRAM according to claim 7 , wherein the first dummy gate structure does not contact the first gate structure, the fifth gate structure or the sixth gate structure.

9 . The layout pattern of the SRAM according to claim 1 , further comprising:
a first local interconnection layer located between the PG 1 A and the PG 1 B and located on the fin structure included in the PU 1 and the PD 1 ; and a second local interconnection layer located between the PG 2 A and the PG 2 B and located on the fin structure included in the PU 2 and the PD 2 .

10 . The layout pattern of SRAM according to claim 9 , wherein the first local interconnection layer and the second local interconnection layer are arranged along the first direction.

11 . The layout pattern of the SRAM according to claim 1 , wherein the PG 1 A and PG 1 B comprise the same fin structure, and the PG 2 A and PG 2 B comprise another same fin structure.

12 . The layout pattern of the SRAM according to claim 1 , further comprising a first bit line connected to the PG 1 A, a second bit line connected to the PG 1 B, a third bit line connected to the PG 2 A and a fourth bit line connected to the PG 2 B.

13 . A layout pattern of a static random-access memory (SRAM), comprising:
a substrate; four SRAM cell regions, which are arranged in a 2*2 array and form the layout pattern of the SRAM, wherein each SRAM cell region comprises: a plurality of fin structures are located on the substrate, and each fin structure extends along a second direction (Y direction); a plurality of gate structures are located on the substrate, and each gate structure extends along a first direction (X direction) and spans the plurality of fin structures to form a plurality of transistors, wherein the plurality of transistors comprise a first pull-up transistor (PU 1 ), a first pull-down transistor (PD 1 ), a second pull-up transistor (PU 2 ), a second pull-down transistor (PD 2 ), a first access transistor (PG 1 A), a second access transistor (PG 1 B), a third access transistor (PG 2 A) and a fourth access transistor (PG 2 B; a first word line contact pad connected to a gate of the first access transistor (PG 1 A) and a first word line; a second word line contact pad connected to a gate of the second access transistor (PG 1 B) and a second word line, wherein the first word line contact pad and the second word line contact pad do not overlap in the second direction; a third word line contact pad connected to a gate of the third access transistor (PG 2 A) and the first word line; and a fourth word line contact pad connected to a gate of the fourth access transistor (PG 2 B) and the second word line, wherein the third word line contact pad and the fourth word line contact pad do not overlap in the second direction.

14 . The layout pattern of SRAM according to claim 13 , wherein the four SRAM cell regions include a first SRAM cell region, a second SRAM cell region, a third SRAM cell region and a fourth SRAM cell region, wherein the first SRAM cell region and the second SRAM cell region are aligned in the first direction, and the first SRAM cell region and the fourth SRAM cell region are aligned in the second direction.

15 . The layout pattern of SRAM according to claim 14 , wherein the first SRAM cell region partially overlaps with the second SRAM cell region, and the third word line contact pad in the first SRAM cell region and the first word line contact pad in the second SRAM cell region are the same structure.

16 . The layout pattern of SRAM according to claim 14 , wherein the first SRAM cell region partially overlaps with the second SRAM cell region, and the fourth word line contact pad in the first SRAM cell region and the second word line contact pad in the second SRAM cell region are the same structure.

17 . The layout pattern of the SRAM according to claim 14 , wherein the first SRAM cell region and the third SRAM cell region comprise the same pattern, and the second SRAM cell region and the fourth SRAM cell region comprise the same pattern.

18 . The layout pattern of the SRAM according to claim 17 , wherein the first SRAM cell region and the second SRAM cell region comprise different patterns.

19 . The layout pattern of the SRAM according to claim 13 , wherein

Assignees

• United Microelectronics Corp

Inventors

• Huang Chun-Hsien
• Kuo Yu-Tse
• Wang Shu-Ru
• Huang Li-Ping
• Tseng Chun-Yen

Classifications

• G11C11/413

  Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction · CPC title

• H10B10/18

  Peripheral circuit regions · CPC title

• H10B10/12 Primary

  comprising a MOSFET load element · CPC title

• G11C11/412 Primary

  using field-effect transistors only · CPC title

• G11C5/063 Primary

  Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay · CPC title