Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-2024395615-A1
Application number	US-202418631548-A
Country	US
Kind code	A1
Filing date	Apr 10, 2024
Priority date	May 25, 2023
Publication date	Nov 28, 2024
Grant date	—

Abstract

A method of manufacturing a semiconductor device includes forming a substrate including a structure having a first region and a contact hole exposing the first region, loading the substrate into a process chamber, repeatedly performing two or more times, a deposition process that includes repeatedly applying radio frequency (RF) plasma power to a process gas for a first time duration and not applying the RF plasma power to the process gas for a second time duration, and a soak process that does not use plasma, at a metal-semiconductor compound formation temperature or higher, within the process chamber, and thereby forming a metal-semiconductor compound layer on the first region, a sidewall material layer on a sidewall of the contact hole, and an upper material layer on the structure, performing a removal process of removing at least a portion of the sidewall material layer in the process chamber, and unloading the substrate from the process chamber after performing the removal process.

First claim

1 . A method of manufacturing a semiconductor device, comprising:
forming a structure having a contact hole exposing a first region; and forming a metal-semiconductor compound layer on the first region exposed by the contact hole by performing a semiconductor process at a metal-semiconductor compound formation temperature using process gases, wherein the process gases include a first process gas containing a metal element and a second process gas generating plasma by plasma power applied to the second process gas, and wherein the forming the metal-semiconductor compound layer includes:
performing a first process of exposing the structure to the process gases in a state in which the plasma power is turned off;
after the first process, repeating, two or more times, a second process and a third process following the second process, wherein the second process comprises repeatedly alternating between a plasma process for a first duration in which the plasma power is turned on and a process of exposing the structure to the process gases for a second duration in which the plasma power is turned off, and the third process comprises exposing the structure to the process gases while the plasma power is turned off; and
after repeating the second process and the third process two or more times, performing a fourth process of exposing the structure to the process gases while the plasma power is turned off.

2 . The method of claim 1 , further comprising forming a preliminary sidewall material layer and a preliminary upper material layer,
wherein at least a portion of the contact hole has an inclined sidewall, wherein the preliminary sidewall material layer covers the inclined sidewall of the contact hole and the preliminary upper material layer covers an upper surface of the structure, wherein the preliminary sidewall material layer and the preliminary upper material layer are formed by repeating the second process and the third process two or more times while the metal-semiconductor compound layer is formed, wherein the thickness of the preliminary upper material layer is greater than the thickness of the preliminary sidewall material layer, wherein the thickness of the preliminary upper material layer is reduced by the fourth process and forms an upper material layer remaining on the upper surface of the structure, and wherein at least a portion of the preliminary sidewall material layer is removed by the fourth process.

3 . The method of claim 2 , further comprising forming a conductive material layer in the contact hole after forming the metal-semiconductor compound layer,
wherein the conductive material layer is in contact with at least a portion of the inclined sidewall of the contact hole.

4 . The method of claim 2 , further comprising forming a conductive material layer in the contact hole after forming the metal-semiconductor compound layer,
wherein the preliminary sidewall material layer is formed of a sidewall material layer having a thickness reduced to 1 nm or less by the fourth process, and wherein the sidewall material layer remains between a sidewall of the contact hole and the conductive material layer.

5 . The method of claim 1 , wherein the process gases further include a third process gas,
wherein the first process gas includes TiCl 4 gas, wherein the second process gas includes Ar gas, and wherein the third process gas includes H 2 gas.

6 . The method of claim 5 , wherein the metal-semiconductor compound layer includes TiSi.

7 . The method of claim 5 , wherein the process gases further include a fourth process gas containing nitrogen, and
wherein the metal-semiconductor compound layer includes a TiSiN layer.

8 . The method of claim 1 , wherein the metal-semiconductor compound formation temperature is in a range of 400° C. to 600° C.

9 . The method of claim 1 , wherein the second process has a duty ratio in a range of 10% to 50%, and
wherein the duty ratio is a ratio of the duration in which the plasma power is turned on to the duration of the second process.

10 . The method of claim 1 , wherein the duration of the third process is 50 to 1000 times greater than the duration of the state in which the plasma power is turned off in the second process.

11 . The method of claim 1 , wherein the duration of the third process is in a range of 3 seconds to 6 seconds.

12 . The method of claim 1 further comprising:
forming at least one conductive material layer on the structure; and
forming a bit line by patterning the at least one conductive material layer, wherein the structure includes a lower structure and a first structure on the lower structure,
wherein the lower structure includes:
a semiconductor substrate;
an active region on the semiconductor substrate;
an isolation region disposed on the semiconductor substrate and disposed on a side surface of the active region;
a gate trench crossing the active region and extending into the isolation region;
a gate structure in the gate trench; and
a first source/drain region and a second source/drain region disposed in the active region on both sides of the gate structure and spaced apart from each other,

wherein the first structure has the contact hole exposing at least a portion of the first source/drain region,
wherein the first region is the first source/drain region,
wherein the metal-semiconductor compound layer is in contact with the first source/drain region, and
wherein the bit line is electrically connected to the metal-semiconductor compound layer.

13 . The method of claim 1 , further comprising:
forming at least one conductive material layer on the structure and in contact with the metal-semiconductor compound layer; patterning the at least one conductive material layer; and forming a data storage structure on the patterned at least one conductive material layer, wherein the structure includes:
a cell transistor including a first source/drain region, a second source/drain region, and a gate electrode;
a bit line electrically connected to the first source/drain region;
a contact plug electrically connected to the second source/drain region; and
the contact hole exposing at least a portion of the contact plug,
wherein the first region is the contact plug, and wherein the metal-semiconductor compound layer is in contact with the contact plug.

14 . A method of manufacturing a semiconductor device, comprising:
forming a substrate including a structure having a first region and a contact hole exposing the first region; loading the substrate into a process chamber; repeatedly performing two or more times, a deposition process that includes repeatedly applying radio frequency (RF) plasma power to a process gas for a first duration and not applying the radio frequency (RF) plasma power to the process gas for a second duration, and a soak process that does not use plasma, at a metal-semiconductor compound formation temperature or higher, within the process chamber, thereby forming a metal-semiconductor compound layer on the first region, a sidewall material layer on a sidewall of the contact hole, and an upper material layer on the structure; performing a removal process of removing at least a portion of the sidewall material layer in the process chamber; and unloading the substrate from the process chamber after performing the removal process.

15 . The method of claim 14 , wherein the deposition process has a duty ratio in a range of 10% to 50%, and
wherein the duty ratio is a ratio of the duration when the RF plasma power is turned on to the duration of the deposition proces

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Seokwon
• Kuh Bongjin
• Kim Sukhoon
• Park Jiho
• Yu Sanghyeok
• Ha Yongho
• Hasan Musarrat

Classifications

• H10W20/40

  Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes · CPC title

• H10W20/054

  by selectively removing parts thereof (H10W20/034 takes precedence) · CPC title

• H10W20/082

  the openings being tapered via holes · CPC title

• H10W20/20

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W74/117

  the substrate having spherical bumps for external connection · CPC title