Power management techniques

Patent metadata

Field	Value
Publication number	US-2024393966-A1
Application number	US-202418733191-A
Country	US
Kind code	A1
Filing date	Jun 4, 2024
Priority date	Aug 9, 2021
Publication date	Nov 28, 2024
Grant date	—

Abstract

Methods, systems, and devices for power management techniques are described. A memory system may receive a command to exit a first power mode and enter a second power mode. The first power mode may have a lower power consumption than the second power mode. The memory system may determine whether a duration of an idle period associated with the first power mode satisfies a threshold based on receiving the command to exit the first power mode. The memory system may receive another command associated with executing a flush operation and perform one or more power management operations based on receiving the command and determining that the duration satisfies the threshold.

First claim

1 . (canceled)

2 . A memory system, comprising:
one or more memory devices; and one or more controllers coupled with the one or more memory devices and configured to cause the memory system to:
receive a first command to enter a first mode of operation;
receive a second command to exit the first mode of operation and enter a second mode of operation, the first mode of operation having a lower power consumption than the second mode of operation mode;
determine, in response to receiving the second command, a threshold in accordance with a duration between entering the first mode of operation and exiting the first mode of operation; and
perform, before receiving a third command to enter a third mode of operation, one or more power management operations associated with entering the third mode of operation in response to comparing a second duration of an idle period to the threshold.

3 . The memory system of claim 2 , wherein the one or more controllers are further configured to cause the memory system to:
activate a timer associated with the idle period in response to receiving the first command; and deactivate the timer in response to receiving the second command, wherein determining the threshold is in accordance with activating the timer and deactivating the timer.

4 . The memory system of claim 2 , wherein the one or more controllers are further configured to cause the memory system to:
receive, before receiving the third command, a fourth command to perform a flush operation.

5 . The memory system of claim 4 , wherein the one or more controllers are further configured to cause the memory system to:
perform the flush operation associated with a cache of the memory system in response to receiving the fourth command, wherein performing the one or more power management operations is in response to performing the flush operation.

6 . The memory system of claim 2 , wherein the one or more controllers are further configured to cause the memory system to:
receive the third command to enter the third mode of operation after performing the one or more power management operations.

7 . The memory system of claim 2 , wherein the one or more controllers are further configured to cause the memory system to:
transfer information stored in a volatile memory device of the memory system to a non-volatile memory device of the memory system; and deactivate the volatile memory device in response to transferring the information from the volatile memory device to the non-volatile memory device.

8 . The memory system of claim 2 , wherein:
the first mode of operation comprises a hibernation mode; the second mode of operation comprises an active mode; and the third mode of operation comprises a sleep mode.

9 . The memory system of claim 2 , wherein the threshold corresponds to a target duration for the third mode of operation.

10 . The memory system of claim 2 , wherein the third mode of operation is associated with a lower power mode than the first mode of operation.

11 . A memory system, comprising:
one or more memory devices; and one or more controllers coupled with the one or more memory devices and configured to cause the memory system to:
receive a first command to perform a flush operation;
perform, after performing the flush operation and before receiving a second command to enter a sleep mode, one or more power management operations associated with entering the sleep mode in accordance with the first command being a command to perform the flush operation and in accordance with a duration of an idle period satisfying a threshold; and
receive the second command to enter the sleep mode after performing the one or more power management operations associated with entering the sleep mode.

12 . The memory system of claim 11 , wherein the one or more controllers are further configured to cause the memory system to:
deactivate a first portion of one or more components associated with the memory system in response to performing the one or more power management operations, wherein receiving the second command is in accordance with deactivating the first portion of the one or more components; and deactivate a second portion of the one or more components in response to receiving the second command.

13 . The memory system of claim 11 , wherein the one or more controllers are further configured to cause the memory system to:
receive a third command to enter a hibernation mode; and activate a timer associated with the idle period in response to receiving the third command, wherein determining whether the duration satisfies the threshold is in accordance with activating the timer.

14 . The memory system of claim 13 , wherein the one or more controllers are further configured to cause the memory system to:
receive a fourth command to exit the hibernation mode; and deactivate the timer associated with the idle period in response to receiving the fourth command, wherein determining whether the duration satisfies the threshold is in accordance with deactivating the timer.

15 . The memory system of claim 14 , wherein:
the third command comprises an enter hibernate command; and the fourth command comprises an exit hibernate command.

16 . The memory system of claim 11 , wherein the one or more controllers are further configured to cause the memory system to:
store, in a register, a value of the duration of the idle period in accordance with determining the duration of the idle period, wherein determining whether the duration satisfies the threshold is in accordance with storing the value.

17 . The memory system of claim 11 , wherein the one or more controllers are further configured to cause the memory system to:
perform clock gating on one or more components, deactivate a volatile memory device associated with the memory system, deactivate one or more components of the memory system, or a combination thereof.

18 . The memory system of claim 11 , wherein the one or more controllers are further configured to cause the memory system to:
transfer information stored in a volatile memory device of the memory system to a non-volatile memory device of the memory system; and deactivate the volatile memory device in response to transferring the information.

19 . The memory system of claim 11 , wherein:
the first command comprises a sync cache command; and the second command comprises a start stop unit command.

20 . A method, comprising:
receiving a first command to enter a first mode of operation; receiving a second command to exit the first mode of operation and enter a second mode of operation, the first mode of operation having a lower power consumption than the second mode of operation mode; determining, in response to receiving the second command, a threshold in accordance with a duration between entering the first mode of operation and exiting the first mode of operation; and performing, before receiving a third command to enter a third mode of operation, one or more power management operations associated with entering the third mode of operation in response to comparing a second duration of an idle period to the threshold.

21 . The method of claim 20 , further comprising:
activating a timer associated with the idle period in response to receiving the first command; and deactivating the timer in response to receiving the second command, wherein determining the threshold is in accordance with activating the timer and deactivating the timer.

Assignees

• Micron Technology Inc

Inventors

• Porzio Luca
• Papa Paolo
• Attanasio Crescenzo

Classifications

• G06F3/0679 Primary

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F12/10

  Address translation · CPC title

• G06F12/0804

  with main memory updating (G06F12/0806 takes precedence) · CPC title

• G06F2212/1028

  Power efficiency · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title