Method of operating circuit, and semiconductor device

Patent metadata

Field	Value
Publication number	US-2024387508-A1
Application number	US-202418785893-A
Country	US
Kind code	A1
Filing date	Jul 26, 2024
Priority date	Sep 14, 2021
Publication date	Nov 21, 2024
Grant date	—

Abstract

A method includes receiving a first power voltage at a gate and first terminal of a first transistor having a second terminal connected to a first node, the first power being gated to provide voltage in a first or a second state; receiving a voltage at a gate of a second transistor coupled between the first node and a ground node; receiving a second power voltage at a follower circuit coupled to the first node; turning on the second transistor to pull the first node toward ground, when the first power voltage is in the first state; turning off the second transistor when the first power voltage is in the second state; and discharging parasitic noise voltage of the first node through the first transistor during at least part of a period in which the first power voltage is in the second state and less than the second power voltage.

First claim

What is claimed is:

1 . A method of operating a circuit to discharge a parasitic noise voltage, the method comprising:
receiving a voltage of a first power supply at a gate of a first transistor and a first terminal of the first transistor, wherein:
the first transistor has a second terminal connected to a first node, and
the first power supply is gated to provide a voltage in a first state or a second state at the gate of the first transistor and the first terminal of the first transistor;
receiving a first gate voltage at a gate of a second transistor coupled between the first node and a first reference node, the first reference node having a ground voltage; receiving a voltage of a second power supply at a follower circuit coupled to the first node; turning on the second transistor to pull a voltage level of the first node toward ground, when the voltage of the first power supply is in the first state; turning off the second transistor when the voltage of the first power supply is in the second state; and discharging a parasitic noise voltage of the first node through the first transistor during at least part of a first period in which the voltage of the first power supply is in the second state and less than the voltage of the second power supply.

2 . The method of claim 1 , wherein:
the first transistor is PMOS transistor that is diode-connected with a cathode connected to the first power supply and an anode connected to the first node, and is forward biased during the at least part of the first period in which the voltage of the first power supply is less than the voltage of the second power supply, and the second transistor is an NMOS transistor.

3 . The method of claim 1 , wherein:
the first state of the first power supply is a positive voltage, and the second state of the first power supply is a ground voltage, the first transistor is a PMOS transistor that is diode-connected with a cathode connected to the first power supply and an anode connected to the first node, and is reverse biased during at least part of a second period in which the voltage of the first power supply is in the first state, and the second transistor is an NMOS transistor.

4 . A semiconductor device, comprising:
a first transistor having a gate connected to a first power supply and a first terminal connected to the first power supply, and a having second terminal connected to a first node; a second transistor having a first terminal connected to the first node, and having a second terminal connected to ground; and a follower circuit connected to the first node and a second power supply, wherein:
the first power supply is turned off to the first transistor and the second transistor during at least part of a period in which the second power supply is turned on to the follower circuit, and
the first node is parasitically capacitively coupled to the second power supply.

5 . The semiconductor device of claim 4 , wherein:
the first transistor is a PMOS transistor connected as a diode, with a cathode connected to the first power supply and an anode connected to the first node, and the second transistor is an NMOS transistor.

6 . The semiconductor device of claim 4 , wherein:
a voltage of the first power supply is less than a voltage of the second power supply during the at least part of a period in which the second power supply is turned on to the follower circuit.

7 . The semiconductor device of claim 4 , wherein:
the first power supply is connected to ground when the first power supply is turned off to the second transistor and the first transistor.

8 . The semiconductor device of claim 4 , wherein:
the second terminal of the first transistor and the first terminal of the second transistor are maintained at a same potential.

9 . A semiconductor device, comprising:
a first active region; a second active region, the second active region being spaced apart from the first active region in a first direction; a first gate electrode segment extending in the first direction and crossing the first active region; a second gate electrode segment extending in the first direction and crossing the second active region; a first conductor extending in the first direction, and in electrical contact with the first active region and the second active region at a first side of the first and second gate electrode segments, the first conductor being spaced apart from the first and second gate electrode segments in a second direction; a second conductor extending in the first direction, and in electrical contact with the first active region at a second side of the first gate electrode segment, the second conductor being spaced apart from the first gate electrode segment in the second direction; and a third conductor extending in the first direction, and in electrical contact with the second active region at the second side of the second gate electrode segment, the second conductor being spaced apart from the second gate electrode segment in the second direction, wherein:
the second conductor is coupled to a first power supply, and is in electrical contact with the first gate electrode segment,
the third conductor is coupled to a ground,
the first conductor is coupled to a follower circuit that receives a voltage from a second power supply, and is parasitically capacitively coupled to the second power supply, and
the first power supply is turned off to the second conductor during at least part of a period in which the second power supply is turned on to the follower circuit.

10 . The semiconductor device of claim 9 , wherein:
the first gate electrode segment is aligned with the second gate electrode segment along the first direction.

11 . The semiconductor device of claim 10 , wherein:
the first gate electrode segment and the second gate electrode segment are integral with one another.

12 . The semiconductor device of claim 10 , wherein:
the first gate electrode segment is spaced apart from the second gate electrode segment in the first direction.

13 . The semiconductor device of claim 9 , further comprising:
a first dummy gate electrode at the first side of the second gate electrode segment; and a second dummy gate electrode at the second side of the second gate electrode segment.

14 . The semiconductor device of claim 13 , wherein:
the first conductor is between the second gate electrode segment and the first dummy gate electrode.

15 . The semiconductor device of claim 13 , wherein:
the first gate electrode segment, the first conductor, and the second conductor each vertically overlap the first active region, the second gate electrode segment, the first conductor, and the third conductor each vertically overlap the second active region, and the first dummy gate electrode and the second dummy gate electrode do not vertically overlap the first active region and do not vertically overlap the second active region.

16 . The semiconductor device of claim 13 , wherein:
the first dummy gate electrode and the second dummy gate electrode are not included in a functional transistor.

17 . The semiconductor device of claim 9 , wherein:
the first active region is doped with a first dopant and the second active region is doped with a second dopant different from the first dopant.

18 . The semiconductor device of claim 9 , wherein:
the first active region is doped with one of an N-type dopant and a P-type dopant, and the second active region is doped with the other of the N-type dopant and the P-type d

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Tsmc China Company Ltd

Inventors

• Zhou Kai
• Ma Yaqi
• Li Wei
• Jin Yongliang
• Chen Cuncun

Classifications

• H10W20/427

  Power or ground buses · CPC title

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title

• H10D84/0165

  the components including complementary IGFETs, e.g. CMOS devices · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D89/601 Primary

  for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs · CPC title