Semiconductor device, manufacturing method, and memory system

Patent metadata

Field	Value
Publication number	US-2024387402-A1
Application number	US-202318484286-A
Country	US
Kind code	A1
Filing date	Oct 10, 2023
Priority date	May 18, 2023
Publication date	Nov 21, 2024
Grant date	—

Abstract

Examples of the present disclosure provide a semiconductor device, a manufacturing method thereof, and a memory system. The semiconductor device comprises: a stacking structure comprising a memory array area and a first sealing area; and at least one circle of sealing structure in the first sealing area and surrounding the memory array area, wherein the sealing structure comprises a sealing ring body penetrating through the stacking structure and at least two circles of first dummy interconnection structures connected with the sealing ring body.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a stacking structure comprising a memory array area and a first sealing area; and at least one circle of sealing structure in the first sealing area and surrounding the memory array area, wherein the sealing structure comprises a sealing ring body penetrating through the stacking structure and at least two circles of first dummy interconnection structures connected with the sealing ring body.

2 . The semiconductor device according to claim 1 , further comprising:
a peripheral device structure comprising: a device area provided with a peripheral device;
and a second sealing area; and
at least two circles of second dummy interconnection structures in the second sealing area and respectively bonded and connected with the at least two circles of first dummy interconnection structures.

3 . The semiconductor device according to claim 1 , wherein the memory array area comprises a core area and a non-core area, the stacking structure comprises a plurality of dielectric layers and a plurality of gate layers alternately stacked in the core area and a first area of the non-core area, and the stacking structure comprises the plurality of dielectric layers and a plurality of gate sacrificial layers alternately stacked in a second area of the non-core area, and wherein the semiconductor device further comprises:
a plurality of contact structures in the second area, wherein the plurality of contact structures respectively extend to gate sacrificial layers of different layers and each of the plurality of contact structures is connected with the gate layer of the same layer as the corresponding gate sacrificial layer in the core area through the gate layer of the same layer as the corresponding gate sacrificial layer in the first area; and a first interconnection structure in contact with the contact structure, wherein the first interconnection structure is of the same material as the first dummy interconnection structure.

4 . The semiconductor device according to claim 3 , wherein the core area comprises a channel structure penetrating through the stacking structure, wherein the semiconductor device further comprises:
a channel contact in contact with an end of the channel structure; and a second interconnection structure in contact with the channel contact, wherein the second interconnection structure is of the same material as the first interconnection structure and the first dummy interconnection structure.

5 . The semiconductor device according to claim 4 , wherein each of the contact structures comprises:
a conductive plug in contact with the first interconnection structure; a first conductive portion in a layer of gate sacrificial layer in the second area and connected with the gate layer of the same layer as the layer of gate sacrificial layer in the core area through the gate layer of the same layer as the layer of gate sacrificial layer in the first area; and a second conductive portion in contact with the conductive plug and the first conductive portion and penetrating through the stacking structure of a corresponding number of layers.

6 . The semiconductor device according to claim 5 , wherein the conductive plug is of the same material as the channel contact.

7 . The semiconductor device according to claim 5 , wherein the contact structure further comprises:
a first filling portion filled in a space enclosed by the conductive plug, the first conductive portion and the second conductive portion.

8 . The semiconductor device according to claim 4 , wherein the sealing ring body comprises:
a metal layer penetrating through the stacking structure; and
a metal plug in contact with the metal layer, wherein the metal plug is in the same layer and of the same material as the channel contact.

9 . The semiconductor device according to claim 8 , wherein the sealing ring body further comprises:
a second filling portion filled in a space enclosed by the metal layer and the metal plug.

10 . The semiconductor device according to claim 4 , wherein the first dummy interconnection structure, the first interconnection structure and the second interconnection structure each comprise at least one layer of through-hole structure and at least one layer of interconnect line structure alternately arranged in a stacking direction, and the numbers of layers of the through-hole structures in the first dummy interconnection structure, the first interconnection structure and the second interconnection structure are the same, and the numbers of layers of the interconnection structures in the first dummy interconnection structure, the first interconnection structure and the second interconnection structure are the same.

11 . A manufacturing method of a semiconductor device, comprising:
forming a stacking structure comprising a memory array area and a first sealing area; and forming at least one circle of sealing structure in the first sealing area of the stacking structure, wherein the at least one circle of sealing structure surrounds the memory array area, and the sealing structure comprises a sealing ring body penetrating through the stacking structure and at least two circles of first dummy interconnection structures connected with the sealing ring body.

12 . The manufacturing method according to claim 11 , further comprising:
forming a peripheral device in a device area of a peripheral device structure; forming, in a second sealing area of the peripheral device structure, second dummy interconnection structures matching positions and numbers of the first dummy interconnection structures; and bonding and connecting the first dummy interconnection structures and the second dummy interconnection structures.

13 . The manufacturing method according to claim 11 , wherein forming the stacking structure comprising the memory array area and the first sealing area comprises:
forming an initial stacking structure comprising the memory array area and the first sealing area, wherein the initial stacking structure comprises a dielectric layer and a gate sacrificial layer sequentially stacked, and the memory array area comprises a core area and a non-core area; and replacing the gate sacrificial layer in the core area and the gate sacrificial layer in a first area in the non-core area in the initial stacking structure with a gate layer to form the stacking structure.

14 . The manufacturing method according to claim 13 , wherein forming the at least one circle of sealing structure in the first sealing area of the stacking structure comprises:
forming a plurality of contact structures in a second area in the non-core area and the at least one circle of sealing ring body in the first sealing area in the same process, wherein the plurality of contact structures respectively extend to the gate sacrificial layers of different layers, and each of the plurality of contact structures is connected with the gate layer of the same layer as the corresponding gate sacrificial layer in the core area through the gate layer of the same layer as the corresponding gate sacrificial layer in the first area; and forming a plurality of first interconnection structures respectively in contact with the plurality of contact structures and the at least two circles of first dummy interconnection structures in the same process.

15 . The manufacturing method according to claim 14 ,
wherein before replacing the gate sacrificial layer in the core area and the gate sacrificial layer in the first area in the non-core area in the initial stacking structure with the gate layer

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Xie Wei
• Zhang Jing
• Liu Yaqin
• Mei Guozhu
• Liu Lei
• Zhang Kun

Classifications

• H10W90/722

  between stacked chips · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W42/00

  Arrangements for protection of devices (arrangements for thermal protection H10W40/00) · CPC title

• H10W42/121 Primary

  protecting against mechanical damage (H10W76/00, H10W74/00 take precedence) · CPC title

• H10B41/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title