Display mother board, display panel and display apparatus

US2024386821A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2024386821-A1
Application numberUS-202418784866-A
CountryUS
Kind codeA1
Filing dateJul 25, 2024
Priority dateDec 7, 2023
Publication dateNov 21, 2024
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Provided is a display mother board including a plurality of sub-regions. At least two sub-regions are arranged in a first direction. The sub-region includes a display panel including a display region, a wiring region and a step region arranged in the first direction, and test pads. The display panel includes a first panel edge, which is an edge of the step region and extends in a second direction intersecting the first direction. The test pads are located on a side of the first panel edge adjacent to the display region. The sub-region includes at least one first pad group each including a plurality of test pads arranged in a direction different from the second direction. Also provided are a display panel formed by cutting the display mother board and a display apparatus including the display panel.

First claim

Opening claim text (preview).

What is claimed is: 1 . A display mother board, comprising a plurality of sub-regions, wherein at least two of the plurality of sub-regions are arranged in a first direction, and one of the plurality of sub-regions comprises: a display panel comprising a display region, a wiring region, and a step region arranged in the first direction, wherein the display panel comprises a first panel edge, and the first panel edge is an edge of the step region and extends in a second direction intersecting the first direction; and test pads located on a side of the first panel edge adjacent to the display region, wherein one of the plurality of sub-regions comprises at least one first pad group each comprising at least two test pads of the test pads, and the at least two test pads in the first pad group are arranged in a direction different from the second direction. 2 . The display mother board according to claim 1 , wherein one of the plurality of sub-regions further comprises a cutting region surrounding the display panel; and the test pads comprise a first test pad located in the cutting region. 3 . The display mother board according to claim 1 , wherein a length of the wiring region in the second direction is smaller than a width of the display region in the second direction, and is smaller than a length of the step region in the second direction, and at least one of the test pads is located between the step region and the display region. 4 . The display mother board according to claim 1 , wherein one of the plurality of sub-regions comprises a first edge extending along the first direction, the test pads are located on a side of a first straight line away from the first edge adjacent to the first straight line, and the first straight line extends in the first direction and is tangent to the display panel at a point of the display panel closest to the first edge. 5 . The display mother board according to claim 1 , wherein the step region comprises pins, at least one of the pins each is electrically connected to one of the test pads sequentially via a first connection line and a second connection line, the first connection line extends in the step region to the first edge panel, and the second connection line is connected to the first connection line and extends from a side of the first panel edge away from the display region to the test pad connected to the second connection line. 6 . The display mother board according to claim 5 , wherein at least one second connection line is connected to the test pad at a side of the test pad adjacent to the display panel, and/or, at least one second connection line is connected to the test pad at a side of the test pad away from the display panel. 7 . The display mother board according to claim 1 , wherein the display panel further comprises a second panel edge, the second panel edge is the edge of the step region, and an extension direction of the second panel edge forms a first angle with the first direction and forms a second angle with the second direction, the step region comprises pins, at least one of the pins is electrically connected to a test pad of the test pads via a third connection line, the third connection line is located on a side of the first panel edge adjacent to the display region, and the third connection line runs through the second panel edge. 8 . The display mother board according to claim 7 , wherein the step region comprises a chip bonding region and a circuit board bonding region that are arranged in the first direction, the pins comprise a first pin located in the chip bonding region and electrically connected to the test pad via the third connection line, the third connection line connected to the first pin comprises a first line segment and a second line segment, the first line segment extends in the second direction in the step region, and the second line segment is connected to the first line segment and runs through the second panel edge. 9 . The display mother board according to claim 1 , wherein the test pads comprise second test pads, and for a single second test pad, at least part of the second test pad is located in the step region. 10 . The display mother board according to claim 9 , wherein the display panel further comprises a second panel edge, the second panel edge is the edge of the step region, and an extension direction of the second panel edge forms a first angle with the first direction and forms a second angle with the second direction, and the second test pads comprise a first-type second test pad located in the step region, and/or, the second test pads comprise a second-type test pad overlapping with the second panel edge in a direction perpendicular to a plane of the display mother board. 11 . The display mother board according to claim 9 , wherein the display panel further comprises a second panel edge, the second panel edge is the edge of the step region, and an extension direction of the second panel edge forms a first angle with the first direction and forms a second angle with the second direction, and at least two of the second test pads are located adjacent to the second panel edge and are arranged along an extension direction of the second panel edge. 12 . The display mother board according to claim 9 , wherein the step region comprises a middle step region and an edge step region located on two sides of the middle step region in the second direction, and at least some of the second test pads are arranged in an array in the edge step region. 13 . The display mother board according to claim 9 , wherein the step region comprises a chip bonding region and a circuit board bonding region arranged in a first direction, and the sub-region further comprises first alignment marks located on at least one of two sides of the circuit board bonding region in the second direction, and the first alignment mark comprises a first marking line, and the second test pad is located on a side of the first marking line adjacent to the chip bonding region. 14 . The display mother board according to claim 9 , wherein the step region comprises a power supply bus, and at least some of the second test pads overlap with the power supply bus in a direction perpendicular to a plane of the display mother board. 15 . The display mother board according to claim 9 , wherein the step region comprises a power supply bus comprising a hollowed region, and at least part of the second test pads is located in the hollowed region. 16 . The display mother board according to claim 1 , wherein the test pad comprises two first edges opposite to each other, and the first edges of at least some of the test pads are adjacent to each other, and a length h of the first edge satisfies 600 μm<h≤800 μm, and/or, for the test pads whose first edges are adjacent to each other, a distance d between geometric centers of the adjacent test pads satisfies 200 μm<d≤400 μm. 17 . The display mother board according to claim 1 , wherein the at least one first pad group comprises a first pad sub-group, and the test pads in the first pad sub-group are arranged in the first direction. 18 . The display mother board according to claim 1 , wherein the at least one first pad group comprises a second pad sub-group, and an arrangement direction of the test pads in the second pad sub-group is different from the first direction. 19 . A display panel, formed by cutting a display mother board, wherein the display mother board comprises: a plurality of sub-regions, wherein at least two of

Assignees

Inventors

Classifications

  • H10D86/443Primary

    adapted for preventing breakage, peeling or short circuiting · CPC title

  • wherein the TFTs are in active matrices · CPC title

  • G09G3/006Primary

    Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays (testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309) · CPC title

  • Test circuits or failure detection circuits included in a display system, as permanent part thereof · CPC title

  • G09F9/30Primary

    in which the desired character or characters are formed by combining individual elements (panels comprising a number of electrodes in a single cell controlling light arriving from an independent light source, e.g. electro-optical or magneto-optical cell, G02F1/00) · CPC title

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What does patent US2024386821A1 cover?
Provided is a display mother board including a plurality of sub-regions. At least two sub-regions are arranged in a first direction. The sub-region includes a display panel including a display region, a wiring region and a step region arranged in the first direction, and test pads. The display panel includes a first panel edge, which is an edge of the step region and extends in a second directi…
Who is the assignee on this patent?
Wuhan Tianma Micro Electronics Co Ltd, Wuhan Tianma Microelectronics Co Ltd Shanghai Branch
What technology area does this patent fall under?
Primary CPC classification H10D86/443. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu Nov 21 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).