Memory system

Patent metadata

Field	Value
Publication number	US-2024385760-A1
Application number	US-202418788695-A
Country	US
Kind code	A1
Filing date	Jul 30, 2024
Priority date	Sep 22, 2017
Publication date	Nov 21, 2024
Grant date	—

Abstract

According to one embodiment, a memory system includes a nonvolatile memory and a controller electrically connected to the nonvolatile memory. The controller selects a write mode from a first mode in which data having N bits is written per one memory cell and a second mode in which data having M bits is written per one memory cell. N is equal to or larger than one. M is larger than N. The controller writes data into the nonvolatile memory in the selected write mode. The controller selects either the first mode or the second mode at least based on a total number of logical addresses mapped in a physical address space of the nonvolatile memory.

First claim

What is claimed is:

1 . A memory system connectable to a host, the memory system comprising:
a nonvolatile memory including a plurality of memory cells; and a controller configured to write data to the nonvolatile memory in either a first mode or a second mode, a number of bits of data written in a memory cell in the second mode being larger than a number of bits of data written in a memory cell in the first mode, wherein the controller is further configured to:
determine a size of a first region of the nonvolatile memory for writing data in the first mode, based on used storage capacity of the memory system;
write first data, which is received from the host, into the first region in the first mode;
upon a size of an available area in the first region being smaller than a first threshold, determine to write at least part of the first data stored in the first region into a second region of the nonvolatile memory in the second mode; and
write the at least part of the first data stored in the first region into the second region in the second mode.

2 . The memory system according to claim 1 , wherein
the first data include a plurality of pieces of data, and the controller is further configured to prioritize keeping a first piece of the plurality of pieces of data having a first access frequency in the first region over a second piece of the plurality of pieces of data having a second access frequency lower than the first access frequency.

3 . The memory system according to claim 2 , wherein
the prioritization is based on information received from the host.

4 . The memory system according to claim 1 , wherein
the first data include a plurality of pieces of data, and the controller is further configured to:
in response to determining to write the at least part of the first data stored in the first region into the second region of the nonvolatile memory in the second mode, select, from the first region and the second region, a write destination region for each of the plurality of pieces of data based on an access frequency of the each of the plurality of pieces of data.

5 . The memory system according to claim 4 , wherein
information about the access frequency is received from the host.

6 . The memory system according to claim 4 , wherein
the controller is further configured to calculate the access frequency.

7 . The memory system according to claim 4 , wherein
the controller is configured to:
select the first region as the write destination region for a piece with a first access frequency among the plurality of pieces of data; and
select the second region as the write destination region for a piece with a second access frequency among the plurality of pieces of data, the second access frequency being lower than the first access frequency.

8 . The memory system according to claim 1 , wherein
the first data include a plurality of pieces of data, and the controller is further configured to:
in response to determining to write the at least part of the first data stored in the first region into the second region of the nonvolatile memory in the second mode, select, from the first region and the second region, a write destination region for a first piece of the plurality of pieces of data based on an access frequency of the first piece of data.

9 . The memory system according to claim 8 , wherein
the controller is further configured to:
in a case where the access frequency of the first piece of data is higher than or equal to a second threshold, select the first region as the write destination region for the first piece of the plurality of pieces of data; and
in a case where the access frequency of the first piece of data is lower than the second threshold, select the second region as the write destination region for the first piece of the plurality of pieces of data.

10 . The memory system according to claim 1 , wherein
the first data include a plurality of pieces of data, and the controller is further configured to:
in response to determining to write the at least part of the first data stored in the first region into the second region of the nonvolatile memory in the second mode, select, from the plurality of pieces of data, a first piece of data to write into the first region based on an access frequency of at least one of the plurality of pieces of data.

11 . The memory system according to claim 10 , wherein
the controller is configured to:
select a piece of data with high access frequency as the first piece of data.

12 . The memory system according to claim 10 , wherein
the controller is configured to:
select a piece of data with the access frequency higher than a second threshold as the first piece of data.

13 . The memory system according to claim 1 , wherein
the first data include a plurality of pieces of data, and the controller is further configured to:
in response to determining to write the at least part of the first data stored in the first region into the second region of the nonvolatile memory in the second mode, select, from the plurality of pieces of data, a first piece of data to write into the second region based on an access frequency of at least one of the plurality of pieces of data.

14 . The memory system according to claim 13 , wherein
the controller is configured to:
select a piece of data with low access frequency as the first piece of data.

15 . The memory system according to claim 13 , wherein
the controller is configured to:
select a piece of data with the access frequency lower than a second threshold as the first piece of data.

16 . The memory system according to claim 1 , wherein
the second region is for writing data in the second mode.

17 . The memory system according to claim 1 , wherein
the used storage capacity of the memory system is a total number of logical addresses mapped to physical addresses of the nonvolatile memory.

18 . The memory system according to claim 1 , wherein
the used storage capacity of the memory system is a ratio of (A) a total number of logical addresses mapped to physical addresses of the nonvolatile memory to (B) an entire logical address space of the memory system, and the controller is further configured to manage the ratio.

19 . The memory system according to claim 1 , wherein
the controller is configured to write the at least part of the first data stored in the first region into the second region in response to the first region reaching its full capacity.

20 . The memory system according to claim 1 , wherein
the first mode is a single-level-cell (SLC) mode and the second mode is a quad-level-cell (QLC) mode.

Assignees

• Kioxia Corp

Inventors

• Igahara Shunichi
• Hida Toshikatsu
• Suzuki Riki
• Amaki Takehiro
• Nishikawa Suguru
• Kojima Yoshihisa

Classifications

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06F3/061

  Improving I/O performance · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F2212/1044

  Space efficiency improvement · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title