Display substrate and display device

Patent metadata

Field	Value
Publication number	US-2024373674-A1
Application number	US-202218031651-A
Country	US
Kind code	A1
Filing date	Jun 29, 2022
Priority date	Jun 29, 2022
Publication date	Nov 7, 2024
Grant date	—

Abstract

Provided are a display substrate and a display device. The display substrate includes a base substrate and pixel units each including a pixel driving circuit at least including a first and a second thin film transistors; a first semiconductor layer, a first conductive layer, a second conductive layer and a second semiconductor layer are sequentially arranged on the base substrate; the first semiconductor layer includes a first active layer, including a first source region, of the first thin film transistor; the first conductive layer includes a first gate of the first thin film transistor; the second conductive layer includes a first transfer electrode electrically connected to the first source region; the second semiconductor layer includes a second active layer, which includes a second source region, of the second thin film transistor; the second source region is electrically connected to the first transfer electrode.

First claim

1 . A display substrate, comprising a base substrate and a plurality of pixel units disposed on the base substrate, each pixel unit comprises a pixel driving circuit, and the pixel driving circuit at least comprises a first thin film transistor and a second thin film transistor;
the display substrate further comprises a first semiconductor layer, a first conductive layer, a second conductive layer and a second semiconductor layer sequentially arranged on the base substrate, wherein the first semiconductor layer comprises a first active layer of the first thin film transistor, the first active layer comprising a first source region, a first drain region and a first channel region sandwiched between the first source region and the first drain region;
the first conductive layer comprises a first gate of the first thin film transistor;
the second conductive layer comprises a first transfer electrode electrically connected with the first source region through a first connecting via hole; and
the second semiconductor layer comprises a second active layer of the second thin film transistor, the second active layer comprising a second source region, a second drain region and a second channel region sandwiched between the second source region and the second drain region, and the second source region being electrically connected with the first transfer electrode through a second connecting via hole.

2 . The display substrate of claim 1 , wherein the pixel driving circuit further comprises a third thin film transistor and a fourth thin film transistor,
the first semiconductor layer further comprises a third active layer of the third thin film transistor, the third active layer comprising a third source region, a third drain region and a third channel region sandwiched between the third source region and the third drain region; the second conductive layer further comprises a second transfer electrode electrically connected with the third drain region through a third connecting via hole; the second semiconductor layer further comprises a fourth active layer of the fourth thin film transistor, the fourth active layer comprising a fourth source region, a fourth drain region and a fourth channel region sandwiched between the fourth source region and the fourth drain region, and the fourth drain region being electrically connected to the second transfer electrode through a fourth connecting via hole.

3 . The display substrate of claim 2 , wherein the second drain region is electrically connected to the second transfer electrode through a fifth connecting via hole.

4 . The display substrate of claim 2 , wherein orthographic projection of the third active layer and the fourth active layer on the base substrate are at least partially overlapped.

5 . The display substrate of claim 4 , further comprising a third conductive layer located on a side of the second semiconductor layer away from the base substrate, wherein the third conductive layer comprises a fourth gate of the fourth thin film transistor and a second gate of the second thin film transistor.

6 . The display substrate of claim 1 , wherein the pixel driving circuit further comprises a fifth thin film transistor and a sixth thin film transistor;
the display substrate further comprises a third semiconductor layer between the first conductive layer and the second conductive layer; the first semiconductor layer further comprises a sixth active layer of the sixth thin film transistor, the sixth active layer comprising a sixth source region, a sixth drain region and a sixth channel region sandwiched between the sixth source region and the sixth drain region; the third semiconductor layer comprises a fifth active layer of the fifth thin film transistor, the fifth active layer comprising a fifth source region, a fifth drain region and a fifth channel region sandwiched between the fifth source region and the sixth drain region, and the fifth drain region being electrically connected to the sixth drain region through a sixth connecting via hole.

7 . The display substrate of claim 6 , wherein the second conductive layer further comprises a fifth gate of the fifth thin film transistor; and
the first conductive layer further comprises a sixth gate of the sixth thin film transistor, and orthographic projections of the fifth gate and the sixth gate on the base substrate are at least partially overlapped.

8 . The display substrate of claim 1 , wherein the second conductive layer further comprises a first light-shielding pattern, and an orthographic projection of the first light-shielding pattern on the base substrate covers an orthographic projection of the second channel region on the base substrate.

9 . The display substrate of claim 8 , wherein the first light-shielding pattern and the first transfer electrode are connected into one piece.

10 . The display substrate of claim 2 , wherein the pixel driving circuit further comprises a storage capacitor, and the first conductive layer further comprises a first electrode plate of the storage capacitor, the first electrode plate being electrically connected to a third gate of the third thin film transistor.

11 . The display substrate of claim 6 , further comprising a fourth conductive layer between the first conductive layer and the third semiconductor layer, the fourth conductive layer comprising a second electrode plate of the storage capacitor and a first power signal terminal, and the first power signal terminal being electrically connected to the sixth source region of the sixth thin film transistor through a seventh connecting via hole.

12 . The display substrate of claim 11 , further comprising a fifth conductive layer between the second semiconductor layer and the second conductive layer, the fifth conductive layer comprising a data line, and the data line being electrically connected to the fifth source region of the fifth thin film transistor through an eighth connecting via hole.

13 . The display substrate of claim 12 , wherein orthographic projections of the seventh connecting via hole and the eighth connecting via hole on the base substrate are at least partially overlapped.

14 . The display substrate of claim 1 , wherein the pixel unit further comprises a light emitting device, the display substrate further comprises a sixth conductive layer located on a side of the second semiconductor layer away from the base substrate, the sixth conductive layer comprising a first electrode of the light emitting device, the second conductive layer further comprises a third transfer electrode, the first electrode is electrically connected to the third transfer electrode through a ninth connecting via hole, and the third transfer electrode is electrically connected to the first drain region of the first thin film transistor through a tenth connecting via hole.

15 . The display substrate of claim 14 , further comprising a seventh conductive layer between the second semiconductor layer and the sixth conductive layer, the seventh conductive layer comprising an initialization signal line electrically connected to the fourth source region of the fourth thin film transistor through an eleventh connecting via hole.

16 . A display device, comprising the display substrate of claim 1 .

17 . A display device, comprising the display substrate of claim 2 .

18 . A display device, comprising the display substrate of claim 3 .

19 . A display device, comprising the display substrate of claim 4 .

20 . A display device, comprising the d

Assignees

• Boe Technology Group Co Ltd

Inventors

• Liu Wei
• Zhao Meng
• Xu Cheng
• Zhou Dandan
• Gu Renquan
• Du Jianhua
• Wang Chaolu

Classifications

• H10K59/1216

  the pixel elements being capacitors · CPC title

• H10K59/131

  Interconnections, e.g. wiring lines or terminals · CPC title

• H10K59/1213 Primary

  the pixel elements being TFTs · CPC title

• H10K59/123

  Connection of the pixel electrodes to the thin film transistors [TFT] · CPC title

• H10K50/00

  Organic light-emitting devices (integrated devices or assemblies of multiple devices H10K59/00, H10K65/00; organic semiconductor lasers H01S5/36) · CPC title