Semiconductor Device and Manufacturing Method Therefor

Patent metadata

Field	Value
Publication number	US-2024371740-A1
Application number	US-202118553813-A
Country	US
Kind code	A1
Filing date	May 19, 2021
Priority date	May 19, 2021
Publication date	Nov 7, 2024
Grant date	—

Abstract

A semiconductor device includes a first wiring layer, a first semiconductor chip, a second wiring layer, and a second semiconductor chip. In addition, in the semiconductor device, a molding resin layer that molds the first semiconductor chip on the first wiring layer and a molding resin layer that molds the second semiconductor chip on the second wiring layer are formed, and the molding resin layers are integrally formed through a through-hole.

First claim

1 . A semiconductor device comprising:
a first wiring layer in which a first wiring is formed; a first semiconductor chip mounted on the first wiring layer; a second wiring layer that is disposed on the first wiring layer and in which a second wiring is formed; a second semiconductor chip mounted on the second wiring layer; a through-hole formed in the second wiring layer; a molding resin layer that molds the first semiconductor chip on the first wiring layer and a molding resin layer that molds the second semiconductor chip on the second wiring layer, the molding layers being integrally formed through the through-hole; and a through electrode that is formed to penetrate the molding resin layer that molds the first semiconductor chip and connects the first wiring and the second wiring to each other.

2 . The semiconductor device according to claim 1 , wherein the first semiconductor chip and the second semiconductor chip respectively include materials different from each other.

3 . A method for manufacturing a semiconductor device, comprising:
a first step of forming, on a first support substrate, a first wiring layer in which a first wiring is formed; a second step of forming, on the first wiring layer, an auxiliary substrate including an opening in a formation region of the first wiring; a third step of mounting a first semiconductor chip on the first wiring layer in the opening of the auxiliary substrate; a fourth step of forming, on a second support substrate, a second wiring layer in which a second wiring is formed and a through-hole that penetrates the second support substrate is formed outside a formation region of the second wiring; a fifth step of mounting a second semiconductor chip on the second wiring layer; a sixth step of removing the second support substrate from the second wiring layer on which the second semiconductor chip is mounted; a seventh step of disposing, on the auxiliary substrate, the second wiring layer from which the second support substrate is removed; an eighth step of integrally forming a molding resin layer that molds the first semiconductor chip on the first wiring layer and a molding resin layer that molds the second semiconductor chip on the second wiring layer through the through-hole; and a ninth step of forming a through electrode that penetrates the molding resin layer that molds the first semiconductor chip and connects the first wiring and the second wiring to each other.

4 . A method for manufacturing a semiconductor device, comprising:
a first step of forming, on a first support substrate, a first wiring layer in which a first wiring is formed; a second step of mounting a first semiconductor chip on the first wiring layer; a third step of forming a first insulating layer that covers the first semiconductor chip on the first wiring layer; a fourth step of forming, on a second support substrate, a second wiring layer in which a second wiring is formed; a fifth step of mounting a second semiconductor chip on the second wiring layer; a sixth step of forming a second insulating layer that covers the second semiconductor chip on the second wiring layer; a seventh step of removing the second support substrate from the second wiring layer on which the second semiconductor chip covered with the second insulating layer is mounted; an eighth step of disposing, on the first insulating layer, the second wiring layer from which the second support substrate is removed; and a ninth step of forming a through electrode that penetrates the first insulating layer and connects the first wiring and the second wiring to each other.

Assignees

• Nippon Telegraph & Telephone

Inventors

• Araki Yusuke
• Matsuzaki Hideaki
• Shiratori Yuta

Classifications

• H10W74/10

  characterised by their shape or disposition · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/00

  Package configurations · CPC title