Interface circuit and memory controller

Patent metadata

Field	Value
Publication number	US-2024361919-A1
Application number	US-202318225670-A
Country	US
Kind code	A1
Filing date	Jul 24, 2023
Priority date	Apr 25, 2023
Publication date	Oct 31, 2024
Grant date	—

Abstract

An interface circuit includes multiple signal processing devices and a monitor and calibration module. A process monitor monitors a current or a voltage of a test element to generate a process detection result. A temperature monitor monitors an environment temperature to generate a temperature monitored result. A calibration circuit performs calibration operation on a signal processing device according to a preferred reference value subset to adjust a characteristic value of the signal processing device. A compensation control mechanism operation logic selects the preferred reference value subset from multiple reference value subsets according to the process detection result and the temperature monitored result and generates a calibration control signal to control the calibration operation of the calibration circuit. The compensation control mechanism operation logic includes a subset handle interface which generates a subset read control signal and transmits the subset read control signal to a corresponding storage circuit.

First claim

What is claimed is:

1 . An interface circuit, comprising:
a signal processing circuit, configured to process a reception signal received from a host device and a transmission signal to be transmitted to the host device, wherein the signal processing circuit comprises: a plurality of signal processing devices; and a monitor and calibration module, comprising:
a process monitor, configured to monitor a current or a voltage of a test element to generate a process detection result;
a temperature monitor, configured to monitor an environment temperature to generate a temperature monitored result;
a calibration circuit, coupled to at least one of the signal processing devices and configured to perform a calibration operation on the at least one of the signal processing devices according to a preferred reference value subset to adjust a characteristic value of the at least one of the signal processing devices;
a storage module, comprising a plurality of storage circuits, each being configured to store a plurality of reference value subsets; and
a compensation control mechanism operation logic, coupled to the process monitor, the temperature monitor, the calibration circuit and the storage module, and configured to collect the process detection result and the temperature monitored result and select a reference value subset as the preferred reference value subset for the calibration operation from the reference value subsets based on the process detection result and the temperature monitored result and accordingly generate a calibration control signal to control the calibration circuit to perform the calibration operation in response to the calibration control signal,
wherein the compensation control mechanism operation logic comprises:
a subset handle interface, coupled to the storage module and configured to receive and decode a subset selection command, generate a subset read control signal according to a decoding result of the subset selection command and transmit the subset read control signal to one of the storage circuits.

2 . The interface circuit of claim 1 , wherein the interface circuit is configured inside of a memory controller and the signal processing circuit is a Serializer-Deserializer (SerDes).

3 . The interface circuit of claim 1 , wherein the compensation control mechanism operation logic is implemented by a Field Programmable Gate Array (FPGA).

4 . The interface circuit of claim 1 , wherein the compensation control mechanism operation logics further comprises:
a compensation control mechanism selection circuit, comprising a plurality of compensation control mechanism selection logics and configured to select a compensation control mechanism according to the process detection result and/or the temperature monitored result and set the selected compensation control mechanism as a currently-operating compensation control mechanism.

5 . The interface circuit of claim 2 , wherein the compensation control mechanism operation logics is further configured to obtain a preset process parameter of the memory controller which is a first-level process parameter, determine a second-level process parameter according to the preset process parameter and the process detection result, and select the reference value subset as the preferred reference value subset according to the second-level process parameter and the temperature monitored result.

6 . The interface circuit of claim 5 , wherein the first-level process parameter indicates a preliminary process corner classification and the second-level process parameter indicates an advanced process corner classification.

7 . The interface circuit of claim 1 , wherein the calibration circuit is configured to set an initial value utilized by the at least one of the signal processing devices in the calibration operation based on a value in the preferred reference value subset.

8 . The interface circuit of claim 1 , wherein the compensation control mechanism operation logics further comprises:
a calibration handle interface, coupled to the calibration circuit and configured to receive and decode a calibration command and generate the calibration control signal according to a decoding result of the calibration command, and transmit the calibration control signal to the calibration circuit.

9 . The interface circuit of claim 1 , wherein the compensation control mechanism operation logic further comprises:
a monitor handle interface, coupled to the process monitor and the temperature monitor and configured to receive and decode a monitor command, generate a monitor control signal according to a decoding result of the monitor command, and provide the monitor control signal to at least one of the process monitor and the temperature monitor.

10 . A memory controller, coupled to a memory device to control access operations of the memory device, comprising:
a host interface, configured to communicate with a host device and comprising a signal processing circuit to process a reception signal received from the host device and a transmission signal to be transmitted to the host device, wherein the signal processing circuit comprises: a plurality of signal processing devices; and a monitor and calibration module, comprising:
a process monitor, configured to monitor a current or a voltage of a test element to generate a process detection result;
a temperature monitor, configured to monitor an environment temperature to generate a temperature monitored result;
a calibration circuit, coupled to at least one of the signal processing devices and configured to perform a calibration operation on the at least one of the signal processing devices according to a preferred reference value subset to adjust a characteristic value of the at least one of the signal processing devices;
a storage module, comprising a plurality of storage circuits, each being configured to store a plurality of reference value subsets; and
a compensation control mechanism operation logic, coupled to the process monitor, the temperature monitor, the calibration circuit and the storage module, and configured to collect the process detection result and the temperature monitored result and select a reference value subset as the preferred reference value subset for the calibration operation from the reference value subsets based on the process detection result and the temperature monitored result and accordingly generate a calibration control signal to control the calibration circuit to perform the calibration operation in response to the calibration control signal,
wherein the compensation control mechanism operation logic comprises:
a subset handle interface, coupled to the storage module and configured to receive and decode a subset selection command, generate a subset read control signal according to a decoding result of the subset selection command and transmit the subset read control signal to one of the storage circuits.

11 . The memory controller of claim 10 , wherein the signal processing circuit is a Serializer-Deserializer (SerDes).

12 . The memory controller of claim 10 , wherein the compensation control mechanism operation logic is implemented by a Field Programmable Gate Array (FPGA).

13 . The memory controller of claim 10 , wherein the compensation control mechanism operation logics further comprises:
a compensation control mechanism selection circuit, comprising a plurality of compensation control mechanism selection logics and configured to select a compensation control mechanism according to the process detection result and/or the temperature monitored result and set the selected compensation control mechanis

Assignees

• Silicon Motion Inc

Inventors

• Shih Fu-Jen

Classifications

• G06F11/3041

  where the computing system component is an input/output interface (interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units G06F13/00) · CPC title

• G06F11/3058

  Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations (thermal management in cooling arrangements of a computing system G06F1/206) · CPC title

• H03K19/017509

  Interface arrangements · CPC title

• H03K19/00369

  Modifications for compensating variations of temperature, supply voltage or other physical parameters · CPC title

• H03M9/00

  Parallel/series conversion or vice versa (digital stores in which the information is moved stepwise per se G11C19/00) · CPC title