Encryption device and operating method of encryption device

Patent metadata

Field	Value
Publication number	US-2024356726-A1
Application number	US-202418634211-A
Country	US
Kind code	A1
Filing date	Apr 12, 2024
Priority date	Apr 21, 2023
Publication date	Oct 24, 2024
Grant date	—

Abstract

An encryption device includes an encryption core circuit configured to generate output data by performing an encryption operation on input data, and an encryption controller circuit configured to control an operation of the encryption core. The encryption core circuit includes a shiftrow circuit configured to generate shift data by performing a shiftrow operation on the input data, a security circuit configured to generate permutation data by performing a permutation operation including a mixcolumn multiplication operation on the shift data, a mixcolumn addition circuit configured to generate first mid data by performing a mixcolumn addition operation on the permutation data, and a round key addition operation circuit configured to generate the output data by performing a round key addition operation on the first mid data.

First claim

1 . An encryption device, comprising:
an encryption core circuit configured to generate output data by performing an encryption operation on input data; and an encryption controller circuit configured to control an operation of the encryption core circuit, wherein the encryption core circuit comprises: a shiftrow circuit configured to generate shift data by performing a shiftrow operation on the input data; a security circuit configured to generate permutation data by performing a permutation operation including a mixcolumn multiplication operation on the shift data; a mixcolumn addition circuit configured to generate first mid data by performing a mixcolumn addition operation on the permutation data; and a round key addition operation circuit configured to generate the output data by performing a round key addition operation on the first mid data.

2 . The encryption device of claim 1 , wherein
the security circuit comprises a plurality of sub security circuits configured to receive any one of a plurality of pieces of sub shift data generated by dividing the shift data, and generate any one of a plurality of pieces of multiplication data included in sub permutation data by performing the permutation operation on the received sub shift data, wherein the permutation operation includes the mixcolumn multiplication operation on any one of a plurality of mixcolumn multiplication values, and the permutation data includes a plurality of pieces of the sub permutation data.

3 . The encryption device of claim 2 , wherein the sub shift data received by each of the plurality of sub security circuits is different from each other, or each of the plurality of sub security circuits performs the permutation operation on the mixcolumn multiplication values different from each other,
wherein the permutation operation includes the mixcolumn multiplication operation.

4 . The encryption device of claim 3 , wherein each of the plurality of sub security circuits comprises:
a decoder configured to decode the received sub shift data and output a decoded value; a permutation circuit configured to output a selected permutation value based on the decoded value; and an encoder configured to generate the multiplication data by encoding the permutation value to represent a result of the mixcolumn multiplication operation on any one of the plurality of mixcolumn multiplication values.

5 . The encryption device of claim 1 , wherein
the security circuit comprises a plurality of sub security circuits configured to receive any one of a plurality of pieces of sub shift data generated by dividing the shift data, and generate sub permutation data including a plurality of pieces of multiplication data by performing the permutation operation including the mixcolumn multiplication operation on the received sub shift data, the permutation data includes a plurality of pieces of the sub permutation data, each of the plurality of pieces of multiplication data is generated by performing the permutation operation on the sub shift data, and the permutation operation includes the mixcolumn multiplication operation on any one of a plurality of mixcolumn multiplication values.

6 . The encryption device of claim 5 , wherein the sub shift data received by each of the plurality of sub security circuits is different from each other.

7 . The encryption device of claim 6 , wherein each of the plurality of sub security circuits comprises:
a decoder configured to decode the received sub shift data and output a decoded value; a permutation circuit configured to output a selected permutation value based on the decoded value; and a plurality of encoders configured to generate the multiplication data by encoding the permutation value to represent a result of the mixcolumn multiplication operation on any one of the plurality of mixcolumn multiplication values.

8 . The encryption device of claim 6 , wherein each of the plurality of sub security circuits comprises:
a decoder configured to decode a part of the received sub shift data and output a decoded value; a permutation circuit configured to output a selected permutation value based on the decoded value; a plurality of encoders configured to generate the multiplication data by encoding the permutation value to represent a result of the mixcolumn multiplication operation on any one of the plurality of mixcolumn multiplication values; and one or more additional operation circuits configured to generate one or more pieces of multiplication data not generated by the plurality of encoders among the plurality of pieces of multiplication data, based on the multiplication data generated by the plurality of encoders.

9 . The encryption device of claim 1 , further comprising:
a mixcolumn multiplication elimination circuit configured to generate second mid data by performing a mixcolumn multiplication elimination operation on the permutation data, wherein the round key addition operation circuit generates the output data by performing the round key addition operation on the second mid data.

10 . An encryption device, comprising:
an encryption core circuit configured to generate output data by performing a plurality of round operations on input data; and an encryption controller circuit configured to control the encryption core circuit to sequentially perform the plurality of round operations including an initial round operation, an iterative round operation of a preset reference number of times, and a final round operation, wherein the encryption core circuit comprises a shiftrow circuit configured to generate shift data by performing a shiftrow operation on the input data, a security circuit configured to generate permutation data by performing a permutation operation including a mixcolumn multiplication operation on the shift data, a mixcolumn addition circuit configured to generate first mid data by performing a mixcolumn addition operation on the permutation data, and a round key addition operation circuit configured to generate the output data by performing a round key addition operation on the first mid data, and the iterative round operation includes the shiftrow operation, the permutation operation, the mixcolumn addition operation, and the round key addition operation.

11 . The encryption device of claim 10 , wherein
the security circuit comprises a plurality of sub security circuits configured to receive any one of a plurality of pieces of sub shift data generated by dividing the shift data, and generate any one of a plurality of pieces of multiplication data included in sub permutation data by performing the permutation operation on the received sub shift data, wherein the permutation operation includes the mixcolumn multiplication operation on any one of a plurality of mixcolumn multiplication values, and the permutation data includes a plurality of pieces of the sub permutation data.

12 . The encryption device of claim 11 , wherein the sub shift data received by each of the plurality of sub security circuits is different from each other, or each of the plurality of sub security circuits performs the permutation operation on the mixcolumn multiplication values different from each other,
wherein the permutation operation includes the mixcolumn multiplication operation.

13 . The encryption device of claim 12 , wherein each of the plurality of sub security circuits comprises:
a decoder configured to decode the received sub shift data and output a decoded value; a permutation circuit configured to output a selected permutation value based on the decoded value; and an encoder configured to generate the multipli

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Gapkyoung
• Kim Jaehyeok
• Lee Yongki
• Choi Hongmook

Classifications

• H04L9/08

  Key distribution {or management, e.g. generation, sharing or updating, of cryptographic keys or passwords (network architectures or network communication protocols for supporting key management in a packet data network H04L63/06)} · CPC title

• H04L9/06

  the encryption apparatus using shift registers or memories for block-wise {or stream} coding, e.g. DES systems {or RC4; Hash functions; Pseudorandom sequence generators} · CPC title

• H04L2209/122

  Hardware reduction or efficient architectures · CPC title

• H04L9/0631 Primary

  Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms · CPC title

• H04L9/003 Primary

  for power analysis, e.g. differential power analysis [DPA] or simple power analysis [SPA] · CPC title