Tfet with or-and logic function

Patent metadata

Field	Value
Publication number	US-2024347639-A1
Application number	US-202318357172-A
Country	US
Kind code	A1
Filing date	Jul 24, 2023
Priority date	Apr 14, 2023
Publication date	Oct 17, 2024
Grant date	—

Abstract

Disclosed is a TFET with an OR-AND logic function. By arranging a horizontal channel and a vertical channel in different directions, three gates are not connected and will not be affected by each other, and can control the current of a whole channel jointly; when a first gate and a second gate are both at a high level, the TFET will be turned on, and when the first gate and a third gate are both at a high level, the TFET will also be turned on; the horizontal channel not only isolates the second gate from the third gate, but also reduces the strength of coupling between the second gate and the third gate, so only a small current passes through the horizontal channel when the second gate and the third gate are both at a high level, and the TFET will not be turned on at this moment.

First claim

What is claimed is:

1 . A tunnel field-effect transistor (TFET) with an OR-AND logic function comprising a substrate layer, a source region, a drain region and a channel region, and the channel region comprising a vertical channel and a horizontal channel, wherein:
the source region, the vertical channel and the drain region are distributed on the substrate layer from left to right and are all rectangular, lower surfaces of the source region, the vertical channel and the drain region are located at the same plane and are all attached to an upper surface of the substrate layer, upper surfaces of the source region, the vertical channel and the drain region are located at the same plane, front surfaces of the source region, the vertical channel and the drain region are located at the same plane, back surfaces of the source region, the vertical channel and the drain region are located at the same plane, a right surface of the source region is fixed and attached to a left surface of the vertical channel, and a right surface of the vertical channel is fixed and attached to a left surface of the drain region, and the TFET further comprises three metal layers and five gate-oxide layers, the three metal layers are referred to as a first metal layer, a second metal layer and a third metal layer respectively, the five gate-oxide layers are referred to as a first gate-oxide layer, a second gate-oxide layer, a third gate-oxide layer, a fourth gate-oxide layer and a fifth gate-oxide layer respectively, wherein: the first gate-oxide layer is rectangular and is located at a front side of the vertical channel, a lower surface of the first gate-oxide layer is attached to the upper surface of the substrate layer, a left surface of the first gate-oxide layer is aligned with the left surface of the vertical channel, a right surface of the first oxide-gate layer is aligned with the right surface of the vertical channel, and a back surface of the first gate-oxide layer is fixed and attached to the front surface of the vertical channel; the first metal layer is rectangular and is located at a front side of the first gate-oxide layer, a lower surface of the first metal layer is attached to the upper surface of the substrate layer, a left surface of the first metal layer is aligned with the left surface of the vertical channel, a right surface of the first metal layer is aligned with the right surface of the vertical channel, a back surface of the first metal layer is fixed and attached to a front surface of the first gate-oxide layer; the second gate-oxide layer, the third gate-oxide layer, the fourth gate-oxide layer, the fifth gate-oxide layer, the second metal layer, the third metal layer and the horizontal channel are all rectangular and are respectively located at a back side of the vertical channel, the second metal layer, the second gate-oxide layer, the horizontal channel, the third gate-oxide layer and the third metal layer are stacked from top to bottom, left surfaces of the second metal layer, the second gate-oxide layer, the horizontal channel, the third gate-oxide layer and the third metal layer are all aligned with the left surface of the vertical channel, right surfaces of the second metal layer, the second gate-oxide layer, the horizontal channel, the third gate-oxide layer and the third metal layer are all aligned with the right surface of the vertical channel, back surfaces of the second metal layer, the second gate-oxide layer, the horizontal channel, the third gate-oxide layer and the third metal layer are located at the same plane, front surfaces of the second gate-oxide layer, the horizontal channel and the third gate-oxide layer are respectively fixed and attached to the back surface of the vertical channel, the fourth gate-oxide layer is located at a front side of the second metal layer and an upper side of the second gate-oxide layer, a front surface of the fourth gate-oxide layer is fixed and attached to the back surface of the vertical channel, a back surface of the fourth gate-oxide layer is fixed and attached to a front surface of the second metal layer, a left surface of the fourth gate-oxide layer is aligned with the left surface of the second metal layer, a right surface of the fourth gate-oxide layer is aligned with the right surface of the second metal layer, an upper surface of the fourth gate-oxide layer is aligned with an upper surface of the second metal layer, a lower surface of the fourth gate-oxide layer is fixed and attached to an upper surface of the second gate-oxide layer, the fifth gate-oxide layer is located at a front side of the third metal layer and a lower side of the third gate-oxide layer, a front surface of the fifth gate-oxide layer is fixed and attached to the back surface of the vertical channel, a back surface of the fifth gate-oxide layer is fixed and attached to a front surface of the third metal layer, a left surface of the fifth gate-oxide layer is aligned with the left surface of the third metal layer, a right surface of the fifth gate-oxide layer is aligned with the right surface of the third metal layer, an upper surface of the fifth gate-oxide layer is fixed and attached to a lower surface of the third gate-oxide layer, and a lower surface of the fifth gate-oxide layer is fixed and attached to the upper surface of the substrate layer; the second metal layer and the third metal layer are symmetrical in an up-and-down direction, the second gate-oxide layer and the third gate-oxide layer are symmetrical in the up-and-down direction, and the fourth gate-oxide and the fifth gate-oxide layer are symmetrical in the up-and-down direction; and the first metal layer is a first gate of the TFET, the second metal layer is a second gate of the TFET, and the third metal layer is a third gate of the TFET.

2 . The TFET with the OR-AND logic function according to claim 1 , wherein:
the substrate layer is made from silicon; the source region is made from silicon, the doping concentration of the source region is 1*10 21 cm −3 , the height of the source region in the up-and-down direction is 80 nm, the thickness of the source region in a front-and-back direction is 10 nm, the length of the source region in a left-and-right direction is 40 nm; the vertical channel is made from silicon, the doping concentration of the vertical channel is 1*10 14 cm −3 , the height of the vertical channel in the up-and-down direction is 80 nm, the thickness of the vertical channel in the front-and-back direction is 10 nm, and the length of the vertical channel in the left-and-right direction is 40 nm; the horizontal channel is made from silicon, the doping concentration of the horizontal channel is 1*10 14 cm −3 , the height of the horizontal channel in the up-and-down direction is 15 nm, the thickness of the horizontal channel in the front-and-back direction is 30 nm, and the length of the horizontal channel in the left-and-right direction is 40 nm; the drain region is made from silicon, the doping concentration of the drain region is 1*10 20 cm −3 , the height of the drain region in the up-and-down direction is 80 nm, the thickness of the drain region in the front-and-back direction is 10 nm, and the length of the drain region in the left-and-right direction is 40 nm; the first gate-oxide layer is made from silicon dioxide, the height of the first gate-oxide layer in the up-and-down direction is 80 nm, the thickness of the first gate-oxide layer in the front-and-back direction is 2.5 nm, and the length of the first gate-oxide layer in the left-and-right direction is 40 nm; the first metal layer is made from polysilicon, the height of the first metal layer in the up-and-down direction is 80 nm, the thickness of the first metal layer in the front-and-back direction is 10 nm, the length of the first metal layer in the left-and-right direction is 40 nm, and a gate work function o

Assignees

• Univ Wenzhou

Inventors

• Ye Hao
• Wang Pengjun
• Zhang Xuejie
• Shi Yijian
• Li Gang
• Chen Bo
• Shen Zhening

Classifications

• H10D84/853

  comprising FinFETs · CPC title

• H10D62/158

  Dispositions · CPC title

• H10D62/153 Primary

  Impurity concentrations or distributions · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/6733

  Multi-gate TFTs · CPC title