Scan test in a single-wire bus circuit

Patent metadata

Field	Value
Publication number	US-2024345162-A1
Application number	US-202418755800-A
Country	US
Kind code	A1
Filing date	Jun 27, 2024
Priority date	Dec 8, 2021
Publication date	Oct 17, 2024
Grant date	—

Abstract

A Scan test in a single-wire bus circuit is described in the present disclosure. The single-wire bus circuit has only one external pin for connecting to a single-wire bus. Given that multiple physical pins are required to carry out the Scan test, the single-wire bus circuit must provide additional pins required by the Scan test. In embodiments disclosed herein, the single-wire bus circuit includes a communication circuit under test, and a driver circuit coupled to the communication circuit via multiple internal pins. The driver circuit uses a subset of the internal pins as input pins and another subset of the internal pins as output pins to carry out the Scan test in the communication circuit. As a result, it is possible to perform the Scan test without adding additional external pins to the single-wire bus circuit, thus helping to reduce complexity and footprint of the single-wire bus circuit.

First claim

What is claimed is:

1 . A method for testing a communication circuit in a single-wire bus circuit comprising:
coupling a bus pin to a master circuit via a single-wire bus; coupling the communication circuit to the bus pin in a communication mode to carry out normal communications over the single-wire bus; receiving a test initiation command from the master circuit during the communication mode that instructs the communication circuit to switch to a test mode to undergo a test; and decoupling the communication circuit from the bus pin and coupling a driver circuit to the bus pin to thereby perform the test in the communication circuit in response to receiving the test initiation command.

2 . The method of claim 1 , further comprising:
coupling a plurality of test pins in the driver circuit to the communication circuit; and in each of a plurality of test cycles:
providing one or more test input values to a first subset of the plurality of test pins to thereby cause the test to be performed in the communication circuit; and
receiving one or more test output values resulting from the test performed in the communication circuit via a second subset of the plurality of test pins.

3 . The method of claim 2 , further comprising:
decoupling the communication circuit from the bus pin and coupling a test driver circuit in the driver circuit to the bus pin in response to an explicit indication of the test mode; and decoupling the test driver circuit from the bus pin and coupling the communication circuit to the bus pin in response to an explicit indication of the communication mode.

4 . The method of claim 3 , further comprising:
asserting a voltage from the communication circuit on a test mode pin in the driver circuit to provide the explicit indication of the test mode; and de-asserting the voltage on the test mode pin to provide the explicit indication of the communication mode.

5 . The method of claim 4 , wherein:
asserting the voltage comprises asserting the voltage on the test mode pin in response to receiving the test initiation command; and de-asserting the voltage comprises de-asserting the voltage on the test mode pin in response to power cycling of the single-wire bus circuit.

6 . The method of claim 2 , further comprising performing a Scan test in the communication circuit in response to receiving the test initiation command, wherein:
the plurality of test pins comprises a Scan input (SI) pin, a Scan enable (SE) pin, a clock (CLK) pin, and a Scan output (SO) pin; the first subset of the plurality of test pins comprises the SI pin, the SE pin, and the CLK pin; and the second subset of the plurality of test pins comprises the SO pin.

7 . The method of claim 6 , further comprising, in each of the plurality of test cycles:
providing an SI value, an SE value, and a CLK value to the SI pin, the SE pin, and the CLK pin, respectively, to thereby cause the Scan test to be performed in the communication circuit; and receiving an SO value resulting from the Scan test performed in the communication circuit via the SO pin.

8 . The method of claim 7 , further comprising modulating each of the SI value, the SE value, and the SO value as a voltage pulse-width modulation (PWM) value.

9 . The method of claim 7 , further comprising dividing each of the plurality of test cycles to include a first bus symbol, a second bus symbol, and a third bus symbol.

10 . The method of claim 9 , further comprising, in each of the plurality of test cycles:
receiving the SI value in the first bus symbol; receiving the SE value in the second bus symbol; and transmitting the SO value in the third bus symbol.

11 . The method of claim 10 , further comprising, in each of the plurality of test cycles, deriving the CLK value on the third bus symbol.

12 . The method of claim 10 , further comprising, in each of the plurality of test cycles:
receiving the SI value and the SE value corresponding to an immediately succeeding one of the plurality of test cycles; and transmitting the SO value corresponding to an immediately preceding one of the plurality of test cycles.

13 . The method of claim 12 , further comprising, in each of the plurality of test cycles:
determining whether the SO value equals a binary zero or a binary one; activating a current sink in the driver circuit in response to determining that the SO value equals the binary zero; and deactivating the current sink in response to determining that the SO value equals the binary one.

14 . The method of claim 13 , further comprising activating the current sink immediately upon determining that the SO value equals the binary zero.

15 . The method of claim 7 , further comprising dividing each of the plurality of test cycles to include a first bus symbol and a second bus symbol.

16 . The method of claim 15 , further comprising, in each of the plurality of test cycles:
receiving the SI value and the SE value in the first bus symbol; and transmitting the SO value in the second bus symbol.

17 . The method of claim 16 , further comprising, in each of the plurality of test cycles, deriving the CLK value on the second bus symbol.

18 . The method of claim 16 , further comprising in each of the plurality of test cycles:
receiving the SI value and the SE value corresponding to an immediately succeeding one of the plurality of test cycles; and transmitting the SO value corresponding to an immediately preceding one of the plurality of test cycles.

19 . The method of claim 18 , further comprising, in each of the plurality of test cycles:
determining whether the SO value represents a binary zero or a binary one; activate a current sink in the driver circuit in response to determining that the SO value equals the binary zero; and deactivating the current sink in response to determining that the SO value equals the binary one.

20 . The method of claim 17 , wherein:
the SI value and the SE value each equals a binary zero when the first bus symbol comprises a voltage pulse-width modulation (PWM) value modulated with a twenty-five percent duty cycle; the SI value equals the binary zero and the SE value equals a binary one when the first bus symbol comprises the voltage PWM value modulated with a fifty percent duty cycle; and the SI value and the SE value each equals the binary one when the first bus symbol comprises the voltage PWM value modulated with a seventy-five percent duty cycle.

Assignees

• Qorvo Us Inc

Inventors

• Hietala Alexander Wayne
• Ngo Christopher Truong
• Bunch Ryan Lee

Classifications

• G11C2029/5602

  Interface to device under test · CPC title

• G01R31/2884

  using dedicated test connectors, test elements or test circuits on the IC under test (G01R31/2855 takes precedence) · CPC title

• G01R31/2851

  Testing of integrated circuits [IC] (G01R31/317 takes precedence; testing individual devices G01R31/26; testing printed circuits G01R31/2801) · CPC title

• G11C29/32

  Serial access; Scan testing · CPC title

• G01R31/31724

  Test controller, e.g. BIST state machine (for scan test G01R31/318555) · CPC title