Rram circuit and method

Patent metadata

Field	Value
Publication number	US-2024331770-A1
Application number	US-202418743997-A
Country	US
Kind code	A1
Filing date	Jun 14, 2024
Priority date	Jun 1, 2018
Publication date	Oct 3, 2024
Grant date	—

Abstract

A memory circuit includes a bias voltage generator including a first node, a current source coupled between a first power supply node and the first node, and a first transistor and a first resistive device coupled in series between the first node and a power reference node. A drive circuit includes a second node, an amplifier including a first input terminal coupled to the first node and a second input terminal coupled to the second node, and a second transistor coupled between a second power supply node and the second node and including a gate coupled to an output terminal of the amplifier, and a resistive random-access memory (RRAM) device is coupled between the second node and the power reference node.

First claim

What is claimed is:

1 . A memory circuit comprising:
a bias voltage generator comprising:
a first node;
a current source coupled between a first power supply node and the first node; and
a first transistor and a first resistive device coupled in series between the first node and a power reference node;
a drive circuit comprising:
a second node;
an amplifier comprising a first input terminal coupled to the first node and a second input terminal coupled to the second node; and
a second transistor coupled between a second power supply node and the second node and comprising a gate coupled to an output terminal of the amplifier; and
a resistive random-access memory (RRAM) device coupled between the second node and the power reference node.

2 . The memory circuit of claim 1 , wherein
the first transistor comprises a first NMOS transistor, the second transistor comprises a first PMOS transistor, and the first resistive device comprises a polycrystalline silicon material.

3 . The memory circuit of claim 2 , wherein
the bias voltage generator further comprises a second resistive device coupled in series with the first NMOS transistor and the first resistive device between the first node and the power reference node, and the second resistive device comprises a metal.

4 . The memory circuit of claim 2 , wherein
the bias voltage generator further comprises a second PMOS transistor coupled between the first node and the first transistor.

5 . The memory circuit of claim 4 , further comprising:
a third PMOS transistor coupled between the second node and the RRAM device, wherein dimensions of the second PMOS transistor match those of the third PMOS transistor.

6 . The memory circuit of claim 2 , wherein
the bias voltage generator further comprises a second NMOS transistor coupled between the first transistor and the power reference node.

7 . The memory circuit of claim 6 , further comprising:
a third NMOS transistor coupled between the RRAM device and the power reference node, wherein dimensions of the second NMOS transistor match those of the third NMOS transistor.

8 . The memory circuit of claim 1 , wherein
the current source is configured to output a predetermined current level ranging from 50 microamperes (μA) to 500 μA.

9 . A memory circuit comprising:
a bias voltage generator comprising:
a first node;
a current source coupled between a first power supply node and the first node;
a first transistor and a first resistive device coupled in series between the first node and a power reference node; and
a first amplifier comprising a first input terminal coupled to one of a source terminal or a drain terminal of the first transistor;
a drive circuit comprising:
a second node;
a second amplifier comprising a second input terminal coupled to the first node and a third input terminal coupled to the second node; and
a second transistor coupled between a second power supply node and the second node and comprising a gate coupled to an output terminal of the second amplifier; and
a resistive random-access memory (RRAM) device coupled between the second node and the power reference node, wherein the first amplifier further comprises an output terminal coupled to a gate of the first transistor and an input terminal of the RRAM device.

10 . The memory circuit of claim 9 , wherein
the first transistor comprises a first NMOS transistor, the RRAM device comprises a second NMOS transistor comprising a gate coupled to the input terminal of the RRAM device, the second transistor comprises a first PMOS transistor, and the first resistive device comprises a polycrystalline silicon material.

11 . The memory circuit of claim 10 , wherein
the bias voltage generator further comprises a second resistive device coupled in series with the first NMOS transistor and the first resistive device between the first node and the power reference node, and the second resistive device comprises a metal.

12 . The memory circuit of claim 10 , wherein the bias voltage generator further comprises one or both of:
a second PMOS transistor coupled between the first node and the first transistor; or a third NMOS transistor coupled between the first transistor and the power reference node.

13 . The memory circuit of claim 10 , wherein
the first input terminal of the first amplifier comprises an inverting input terminal coupled to the source terminal of the first NMOS transistor, and the bias voltage generator further comprises:
a second resistive device coupled between a non-inverting input terminal of the first amplifier and the drain terminal of the first NMOS transistor; and
a third resistive device coupled between the non-inverting input terminal of the first amplifier and the power reference node.

14 . The memory circuit of claim 10 , wherein
the first input terminal of the first amplifier comprises an inverting input terminal coupled to the source terminal of the first NMOS transistor, and the bias voltage generator further comprises:
a second resistive device coupled between a non-inverting input terminal of the first amplifier and the drain terminal of the first NMOS transistor; and
a third NMOS transistor coupled between the non-inverting input terminal of the first amplifier and the power reference node.

15 . The memory circuit of claim 10 , wherein
the current source is a first current source, the first input terminal of the first amplifier comprises a non-inverting input terminal coupled to the drain terminal of the first NMOS transistor, and the bias voltage generator further comprises:
a second current source coupled between the first power supply node and an inverting input terminal of the first amplifier; and
a second resistive device coupled between the inverting input terminal of the first amplifier and the power reference node.

16 . A method of operating a memory circuit, the method comprising:
generating a bias voltage at a first node by conducting a current from a current source coupled between a first power supply node and the first node through a first transistor and a first resistive device coupled in series between the first node and a power reference node; generating a drive voltage at a second node by receiving the bias voltage at a first input terminal of a first amplifier, receiving the drive voltage at a second input terminal of the first amplifier, and outputting using an output terminal of the first amplifier to control a gate of a second transistor coupled between a second power supply node and the second node; and coupling a resistive random-access memory (RRAM) device to each of the second node and the power reference node.

17 . The method of claim 16 , wherein
the conducting the current through the first transistor comprises conducting the current through a first NMOS transistor, the controlling the gate of the second transistor comprises controlling the gate of a first PMOS transistor, and the conducting the current through the first resistive device comprises conducting the current through a polycrystalline silicon material.

18 . The method of claim 17 , wherein
the conducting the current through the first transistor and the first resistive device coupled in series between the first node and the power reference node comprises conducting the current further through a metal resistive device coupled between the first node and the power reference node.

19 . The method of claim 17 , wherein
the conducting the cu

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chou Chung-Cheng
• Chen Hsu-Shun
• Lai Chien-An
• Tseng Pei-Ling
• Lin Zheng-Jun

Classifications

• G11C13/0069

  Writing or programming circuits or methods · CPC title

• G11C13/004

  Reading or sensing circuits or methods · CPC title

• G11C13/003

  Cell access · CPC title

• G11C2213/74

  Array wherein each memory cell has more than one access device · CPC title

• G11C2213/79

  Array wherein the access device being a transistor · CPC title