Cache processing request for data stored in stack area by using useless information, operating method of cache, and electronic device comprising cache

Patent metadata

Field	Value
Publication number	US-2024320159-A1
Application number	US-202418609664-A
Country	US
Kind code	A1
Filing date	Mar 19, 2024
Priority date	Mar 24, 2023
Publication date	Sep 26, 2024
Grant date	—

Abstract

A cache includes a data memory, a tag memory, and a cache controller. The data memory includes a stack area storing, in a stack structure, data used by an external processor in a plurality of cache lines. The tag memory stores a tag entry including useless information indicating whether data stored in a corresponding cache line has been popped. The cache controller is configured to, when a pop request for data stored in the stack area is received, change the useless information of a cache line storing the data subject to the pop request, to a useless state.

First claim

What is claimed is:

1 . A cache comprising:
a data memory including a stack area storing, in a stack structure, data used by an external processor in a plurality of cache lines; a tag memory for storing a tag entry including useless information indicating whether data stored in a corresponding cache line has been popped; and a cache controller configured to, when a pop request for data stored in the stack area is received, change the useless information of a cache line storing the data subject to the pop request, to a useless state.

2 . The cache of claim 1 , wherein the cache controller is further configured to, when a push request for the cache line in which the useless information is in the useless state is received, change the useless information of the cache line to store the data subject to the push request, to a useful state.

3 . The cache of claim 1 , wherein the cache controller is further configured to, when a read request for the data stored in the stack area is received, set read data based on the useless information of the cache line storing the data subject to the read request.

4 . The cache of claim 3 , wherein the cache controller is further configured to:
when the useless information of the cache line storing the data subject to the read request is in the useless state, set the read data to dummy data different from the data subject to the read request; and when the useless information of the cache line storing the data subject to the read request is in a useful state, set the read data to data stored in the cache line.

5 . The cache of claim 1 , wherein the tag entry further comprises:
valid information indicating whether the data stored in the corresponding cache line is valid; and dirty information indicating whether the data stored in the corresponding cache line is different from data stored in an external main memory.

6 . The cache of claim 5 , wherein the cache controller is further configured to, when an evict operation or a flush operation is performed on the cache line in which the dirty information is in a dirty state and the useless information of the cache line subject to the evict operation or the flush operation is in the useless state, change the valid information of the cache line subject to the evict operation or the flush operation to an invalid state.

7 . The cache of claim 5 , wherein the cache controller is further configured to, when an evict operation or a flush operation is performed on the cache line in which the dirty information is in a dirty state and the useless state of the cache line subject to the evict operation or the flush operation is in a useful state, store, in the main memory, data stored in the cache line subject to the evict operation or the flush operation and change the valid information to an invalid state.

8 . The cache of claim 5 , wherein the cache controller is further configured to, when a push request for the stack area is received, change the valid information of a cache line to store data subject to the push request, to a valid state, and change the dirty information of the cache line to store the data subject to the push request, to a dirty state.

9 . An operating method of a cache comprising a data memory including a stack area storing data in a stack structure, a tag memory, and a cache controller, the operating method comprising:
receiving, by the cache controller, a pop request from a processor; and changing, by the cache controller, useless information in the tag memory for a cache line of the stack area storing data subject to the pop request, to a useless state, wherein the useless information indicates whether data stored in a corresponding cache line has been popped.

10 . The operating method of claim 9 , further comprising:
receiving, by the cache controller, a push request for the cache line in which the useless information is in the useless state; and changing, by the cache controller, the useless information of a cache line to store data subject to the push request, to a useful state.

11 . The operating method of claim 9 , further comprising:
receiving, by the cache controller, a read request for the data stored in the stack area; and setting, by the cache controller, read data based on useless information of a cache line storing the data subject to the read request.

12 . The operating method of claim 11 , wherein the setting of the read data comprises:
when the useless information of the cache line storing the data subject to the read request is in a useless state, setting, by the cache controller, the read data to dummy data different from the data subject to the read request; and when the useless information of the cache line storing the data subject to the read request is in a useful state, setting, by the cache controller, the read data to data stored in the cache line.

13 . The operating method of claim 9 , wherein a tag entry of the tag memory comprises:
valid information indicating whether data stored in a cache line corresponding to a tag address is valid; and dirty information indicating whether the data stored in the cache line corresponding to the tag address is different from data stored in a main memory.

14 . An electronic device comprising:
a main memory; a cache; and a processor, wherein the cache includes: a data memory including a stack area storing, in a stack structure, data used by the processor in a plurality of cache lines; a tag memory for storing a tag entry including information about the data stored in the stack area; and a cache controller configured to process a request for the data stored in the stack area based on the tag entry, the tag entry includes useless information indicating whether data stored in a corresponding cache line has been popped, and the cache controller is further configured to, when a pop request for the data stored in the stack area is received, change the useless information of a cache line storing the data subject to the pop request, to a useless state.

15 . The electronic device of claim 14 , wherein the cache controller is further configured to, when a push request for the cache line in which the useless information is in the useless state is received, change the useless information of the cache line to store data subject to the push request, to a useful state.

16 . The electronic device of claim 14 , wherein the cache controller is further configured to, when a read request for the data stored in the stack area is received, set read data based on the useless information of a cache line storing the data subject to the read request.

17 . The electronic device of claim 16 , wherein the cache controller is further configured to:
when the useless information of the cache line storing the data subject to the read request is in a useless state, set the read data to dummy data different from the data subject to the read request; and when the useless information of the cache line storing the data subject to the read request is in a useful state, set the read data to data stored in the cache line.

18 . The electronic device of claim 14 , wherein the tag entry further comprises:
valid information indicating whether the data stored in the corresponding cache line is valid; and dirty information indicating whether the data stored in the corresponding cache line is different from data stored in the main memory.

19 . The electronic device of claim 18 , wherein the cache controller is further configured to, when an evict operation or

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Moongyung
• Ham Donghyeon
• Eom Youngsik
• Won Euiyeon
• Cho Ara

Classifications

• G06F2212/1016

  Performance improvement · CPC title

• G06F2212/1024

  Latency reduction · CPC title

• G06F12/0804

  with main memory updating (G06F12/0806 takes precedence) · CPC title

• G06F2212/502

  using adaptive policy · CPC title

• G06F2212/451

  Stack data · CPC title