Memory system

Patent metadata

Field	Value
Publication number	US-2024320097-A1
Application number	US-202418590217-A
Country	US
Kind code	A1
Filing date	Feb 28, 2024
Priority date	Mar 20, 2023
Publication date	Sep 26, 2024
Grant date	—

Abstract

A memory system includes a nonvolatile memory; and a controller configured to (i) select one of a plurality of read retry processes having different average required times, respectively, based on reliability of a target area of the nonvolatile memory on which a read process is to be executed and (ii) execute the selected read retry process.

First claim

What is claimed is:

1 . A memory system comprising:
a nonvolatile memory; and a controller configured to (i) select one of a plurality of read retry processes having different average required times, respectively, based on reliability of a target area of the nonvolatile memory on which a read process is to be executed and (ii) execute the selected read retry process.

2 . The memory system according to claim 1 ,
wherein the controller is configured to (i) select a first one of the read retry processes having a first average required time when the reliability of the target area of the read process satisfies a criteria; and (ii) select a second one of the read retry processes having a second average required time that is longer than the first average required time when the reliability of the target area does not satisfy the criteria.

3 . The memory system according to claim 2 ,
wherein the controller is configured to determine whether the reliability of the target area satisfies the criteria based on an indicator related to an area of the nonvolatile memory, wherein the area is larger than the target area and includes the target area.

4 . The memory system according to claim 2 ,
wherein the controller is configured to determine whether the reliability of the target area satisfies the criteria based on an indicator related to an area of the nonvolatile memory, wherein the area is smaller than the target area and is part of the target area.

5 . The memory system according to claim 2 ,
wherein the controller is configured to (i) select the first read retry process when the number of write-and-erase cycles of the target area is smaller than a first threshold and (ii) select the second read retry process when the number of write-and-erase cycles of the target area is larger than the first threshold.

6 . The memory system according to claim 2 ,
wherein the controller is configured to (i) select the first read retry process when the number of times of reading of the target area is smaller than a second threshold and (ii) select the second read retry process when the number of times of reading of the target area is larger than the second threshold.

7 . The memory system according to claim 2 ,
wherein the controller is configured to (i) select the first read retry process when a refresh operation for rewriting data of a first block including the target area to a second block is performed according to elapse of a predetermined period and (ii) select the second read retry process when the refresh operation is performed before elapse of the predetermined period.

8 . The memory system according to claim 2 ,
wherein the controller is configured to (i) select the first read retry process when a time interval of a refresh operation for rewriting data of a first block including the target area to a second block is larger than a third threshold and (ii) select the second read retry process when a time interval of the refresh operation is smaller than the third threshold.

9 . The memory system according to claim 2 ,
wherein the controller is configured to (i) select the first read retry process when an error correction ability to the target area is a first correction ability and (ii) select the second read retry process when the error correction ability to the target area is a second correction ability lower than the first correction ability.

10 . The memory system according to claim 2 ,
wherein the controller is configured to (i) select the first read retry process when temperature during writing in the target area is higher than a fourth threshold and (ii) select the second read retry process when temperature during writing in the target area is lower than the fourth threshold.

11 . The memory system according to claim 2 ,
wherein the controller is configured to (i) select the first read retry process when a word line corresponding to a memory cell including the target area exists at a first position in a block and (ii) select the second read retry process when the word line exists at a second position closer to an end than the first position in the block.

12 . The memory system according to claim 2 ,
wherein the controller is configured to (i) select the first read retry process when elapse time from start-up of the memory system is longer than a fifth threshold and (ii) select the second read retry process when elapse time from start-up of the memory system is shorter than the fifth threshold.

13 . A method of controlling a nonvolatile memory, comprising:
selecting one of a plurality of read retry processes having different average required times, respectively, based on reliability of a target area of the nonvolatile memory on which a read process is to be executed; and executing the selected read retry process.

14 . The method according to claim 13 , further comprising:
selecting a first one of the read retry processes having a first average required time when the reliability of the target area of the read process satisfies a criteria; and selecting a second one of the read retry processes having a second average required time that is longer than the first average required time when the reliability of the target area does not satisfy the criteria.

15 . The method according to claim 14 ,
wherein whether the reliability of the target area satisfies the criteria is determined based on an indicator related to an area of the nonvolatile memory, wherein the area is larger than the target area and includes the target area.

16 . The method according to claim 14 ,
wherein whether the reliability of the target area satisfies the criteria is determined based on an indicator related to an area of the nonvolatile memory, wherein the area is smaller than the target area and is part of the target area.

17 . A controller connectable to a nonvolatile memory, comprising:
a circuit configured to:
select one of a plurality of read retry processes having different average required times, respectively, based on reliability of a target area of the nonvolatile memory on which a read process is to be executed; and
execute the selected read retry process.

18 . The controller according to claim 17 , wherein the circuit is further configured to:
select a first one of the read retry processes having a first average required time when the reliability of the target area of the read process satisfies a criteria; and select a second one of the read retry processes having a second average required time that is longer than the first average required time when the reliability of the target area does not satisfy the criteria.

19 . The controller according to claim 18 ,
wherein the circuit is configured to determine whether the reliability of the target area satisfies the criteria based on an indicator related to an area of the nonvolatile memory, wherein the area is larger than the target area and includes the target area.

20 . The controller according to claim 18 ,
wherein the circuit is configured to determine whether the reliability of the target area satisfies the criteria based on an indicator related to an area of the nonvolatile memory, wherein the area is smaller than the target area and is part of the target area.

Assignees

• Kioxia Corp

Inventors

• Suzuki Riki
• Hida Toshikatsu
• Kojima Yoshihisa

Classifications

• G06F11/141 Primary

  for bus or memory accesses · CPC title

• G06F11/1068

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title

• G06F11/1048 Primary

  using arrangements adapted for a specific error detection or correction feature · CPC title