High density pmut array architecture for ultrasound imaging

Patent metadata

Field	Value
Publication number	US-2024315671-A1
Application number	US-202318123602-A
Country	US
Kind code	A1
Filing date	Mar 20, 2023
Priority date	Mar 20, 2023
Publication date	Sep 26, 2024
Grant date	—

Abstract

A PMUT includes a substrate being doped and having a plurality of conductive vias formed therein, each conductive via formed of a portion of the substrate extending completely from a back side of the substrate to a front side of the substrate and being encircled by an isolating structure that electrically isolates that portion of the substrate from other portions of the substrate. An insulating layer stacked on the front side of the substrate and has through-holes therein over the plurality of conductive vias. An interconnection layer is stacked on the insulating layer and is connected to the plurality of conductive vias. A membrane carried is by the interconnection layer and underlying substrate, the membrane being shaped so as to delimit a chamber. A piezoelectric stack formed on the membrane over the chamber and vibrates the membrane in response to application of an alternating voltage to the piezoelectric stack.

First claim

1 . A device comprising a piezoelectric micromachined ultrasound transducer (PMUT), the PMUT comprising:
a substrate, the substrate having a plurality of conductive vias formed therein, each conductive via comprised of a portion of the substrate extending completely from a back side of the substrate to a front side of the substrate and being encircled by an isolating structure that electrically isolates that portion of the substrate from other portions of the substrate; an insulating layer stacked on the front side of the substrate and having through-holes defined therein over the plurality of conductive vias; an interconnection layer stacked on the insulating layer and being directly electrically connected to the plurality of conductive vias; a membrane carried by the interconnection layer and underlying substrate, the membrane shaped so as to delimit a chamber defined on a top side and sidewalls by the membrane and defined on a bottom side by the insulating layer; and a piezoelectric stack formed on the membrane over the chamber and configured to vibrate the membrane in response to application of an alternating voltage to the piezoelectric stack.

2 . The device of claim 1 , wherein the substrate has a plurality of conductive columns formed therein, each conductive column being the portion of the substrate within each conductive via that extends completely from the back side of the substrate to the front side of the substrate and is encircled by the isolation structure.

3 . The device of claim 2 , wherein each conductive column is comprised of doped polysilicon.

4 . The device of claim 2 , wherein the isolating structure of each via is comprised of oxide.

5 . The device of claim 1 , wherein the insulating layer comprises an oxide layer.

6 . The device of claim 1 , wherein each PMUT further comprises an insulating layer on the back side of the substrate, with electrodes extending through holes in the insulating layer to contact the conductive vias.

7 . The device of claim 1 , further comprising first and second conventional vias formed to extend through the membrane to electrically connect the piezoelectric stack to the interconnection layer.

8 . The device of claim 1 , wherein the membrane comprises: a support layer carried by the interconnection layer and underlying substrate and being shaped so as to delimit the chamber; a permeable polysilicon layer formed on the support layer; and a structural layer carried by the permeable polysilicon layer and underlying portions of the structural layer.

9 . The device of claim 8 , further comprising a silicon thermal oxide layer stacked on the membrane and carrying the piezoelectric stack; wherein the piezoelectric stack comprises a first electrode formed on the silicon thermal oxide layer, a piezoelectric layer formed on the first electrode, and a second electrode formed on the piezoelectric layer, wherein the first electrode is electrically connected to the interconnection layer through a first conventional via extending through the membrane and silicon thermal oxide layer; and wherein the second electrode is electrically connected to the interconnection layer through a second conventional via extending through the membrane and silicon thermal oxide layer.

10 . A method of making a piezoelectric micromachined ultrasound transducer (PMUT), the method comprising:
etching a substrate to define a plurality of conductive columns within the substrate, with the etch defining a ring around each conductive column; depositing an isolating material within each ring to thereby define a plurality of conductive vias, each conductive via including one of the conductive columns and being isolated by the isolating material within the ring associated with that conductive via; depositing an insulating layer on a front side of the substrate; forming an interconnection layer on the insulating layer and extending through the insulating layer to make electrical contact with the plurality of conductive vias; depositing a sacrificial layer on the interconnection layer and patterning the sacrificial layer; forming a membrane layer on the sacrificial layer, with portions of the membrane layer extending through the sacrificial layer to contact the interconnection layer; performing an etch release to remove the sacrificial layer, thereby defining a membrane carried by the interconnection layer and underlying substrate; depositing a ceiling layer on the membrane layer and patterning the ceiling layer; and forming a piezoelectric stack on the ceiling layer and exposed portions of the membrane over a chamber delimited in the membrane.

11 . The method of claim 10 , wherein each conductive column is comprised of doped polysilicon.

12 . The method of claim 10 , wherein the sacrificial layer is patterned to define through-holes in therein exposing portions of the interconnection layer; and wherein the portions of the membrane layer that extend through the sacrificial layer extend through the through-holes.

13 . The method of claim 10 , wherein forming the interconnection layer comprises depositing a polysilicon layer on the insulating layer and patterning the polysilicon layer.

14 . The method of claim 10 , wherein performing the etch release comprising etching through-holes in the membrane layer and then performing the etch release through the through-holes in the membrane layer; and wherein the ceiling layer extends across the through-holes etched in the membrane layer.

15 . The method of claim 14 , wherein the etch release comprises a vapor-phase hydrofluoric acid (vHF) etch.

16 . The method of claim 10 , further comprising grinding a back side of the substrate to expose the plurality of conductive vias.

17 . The method of claim 16 , further comprising:
flipping the substrate; forming an insulating layer on the back side of the substrate and patterning the substrate to expose the plurality of conductive vias; and forming electrodes that extend through the insulating layer on the back side of the substrate to contact the exposed plurality of conductive vias.

18 . The method of claim 10 , wherein forming the piezoelectric stack on the membrane comprises:
depositing a first conductive layer on the membrane and patterning the first conductive layer to thereby form a first electrode; forming a piezoelectric layer on the first conductive layer; depositing a second conductive layer on the piezoelectric layer, the ceiling layer, and exposed portions of the membrane layer, and patterning the second conductive layer to thereby form a second electrode.

19 . The method of claim 10 , wherein the substrate is a highly doped silicon substrate.

20 . The method of claim 10 ,
wherein forming the membrane layer on the sacrificial layer comprises: forming a support layer on the sacrificial layer and patterning the support layer; and forming a permeable polysilicon layer on the support layer; wherein the etch release is performed through the permeable polysilicon layer; and wherein forming the membrane layer further comprises growing a structural layer on the permeable polysilicon layer and patterning the structural layer.

Assignees

• St Microelectronics Int Nv

Inventors

• Vercesi Federico
• Allegato Giorgio
• Afifi Afifi Tarek
• Costantini Sonia

Classifications

• B06B1/0607

  using multiple elements (B06B1/064 and B06B1/0688 take precedence) · CPC title

• A61B8/4494

  characterised by the arrangement of the transducer elements · CPC title

• A61B8/4488 Primary

  the transducer being a phased array · CPC title

• G01H11/08

  using piezoelectric devices · CPC title

• B06B1/0666

  used as a diaphragm · CPC title