Electronic apparatus and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-2024312983-A1
Application number	US-202418671908-A
Country	US
Kind code	A1
Filing date	May 22, 2024
Priority date	Jul 29, 2019
Publication date	Sep 19, 2024
Grant date	—

Abstract

The disclosure provides an electronic apparatus and a manufacturing method thereof. The electronic apparatus includes a first insulating layer, a first metal layer, a second metal layer, a PN junction assembly, and a transistor circuit. The first insulating layer includes a first surface and a second surface opposite to the first surface. The first metal layer is formed above the second surface. The second metal layer is formed on the second surface. The PN junction assembly is disposed on the first surface and electrically connected with the first metal layer and the second metal layer. The PN junction assembly includes a variable capacitor. The transistor circuit is electrically connecting with the second metal layer.

First claim

What is claimed is:

1 . An electrical apparatus, comprising:
a first insulating layer, comprising a first surface and a second surface opposite to the first surface; a first metal layer, formed above the second surface; a second metal layer, formed on the second surface; a PN junction assembly, disposed on the first surface and electrically connected with the first metal layer and the second metal layer, wherein the PN junction assembly comprises a variable capacitor; and a transistor circuit, electrically connected with the second metal layer.

2 . The electronic apparatus as claimed in claim 1 , further comprising:
a routing layer, formed on the second surface and electrically connected with the transistor circuit; and a control circuit, electrically connected with the routing layer.

3 . The electronic apparatus as claimed in claim 1 , wherein the transistor circuit is disposed on the first surface or the second surface.

4 . The electronic apparatus as claimed in claim 1 , wherein the first metal layer has an opening, the first metal layer is formed above the second metal layer, and a projection of the opening on the second surface is overlapped with a projection of the second metal layer on the second surface.

5 . The electronic apparatus as claimed in claim 1 , wherein the first insulating layer comprises a flexible material.

6 . A manufacturing method of an electronic apparatus, comprising:
providing a carrier substrate; forming a first metal layer having an opening on the carrier substrate; forming a first insulating layer on the first metal layer, and a first surface of the first insulating layer contacts the first metal layer; and forming a second metal layer on the first insulating layer, and a second surface of the first insulating layer contacts the second metal layer, wherein the first surface is opposite to the second surface, and a projection of the opening on the second surface is overlapped with a projection of the second metal layer on the second surface.

7 . The manufacturing method as claimed in claim 6 , further comprising:
forming a transistor circuit on the first insulating layer; forming a routing layer on the first insulating layer, and electrically connecting the routing layer with the transistor circuit; forming a second insulating layer covering the second metal layer, the transistor circuit, and the routing layer on the first insulating layer; disposing an electronic assembly on the second insulating layer, and electrically connecting the electronic assembly with the transistor circuit, the first metal layer, and the second metal layer; and electrically connecting a control circuit with the routing layer.

8 . The manufacturing method as claimed in claim 6 , further comprising:
forming a routing layer on the first insulating layer; forming a second insulating layer covering the second metal layer and the routing layer on the first insulating layer; disposing the transistor circuit on the second insulating layer and electrically connecting the transistor circuit with the routing layer; disposing an electronic assembly on the second insulating layer, and electrically connecting the electronic assembly with the transistor circuit, the first metal layer, and the second metal layer; and electrically connecting a control circuit with the routing layer.

Assignees

• Innolux Corp

Inventors

• Hung Tang Chin
• Ting Chin-Lung
• Wei Chung-Kuang
• Kao Ker-Yih
• Wang Tong-Jung
• Hsieh Chih-Yung
• Huang Hao Jung
• Li I-Yin
• Ho Chia-Chi
• Lin Yi Hung
• Chou Cheng-Hsu
• Tseng Chia-Ping

Classifications

• H10W70/614

  the multiple chips being integrally enclosed · CPC title

• H10W90/10

  Configurations of laterally-adjacent chips · CPC title

• H10W90/401

  characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title

• H10W70/611 Primary

  for connecting multiple chips together · CPC title

• H10W20/496

  Capacitor integral with wiring layers · CPC title