Semiconductor devices and methods of fabricating the same

Patent metadata

Field	Value
Publication number	US-2024297232-A1
Application number	US-202418655409-A
Country	US
Kind code	A1
Filing date	May 6, 2024
Priority date	Jan 10, 2020
Publication date	Sep 5, 2024
Grant date	—

Abstract

A semiconductor device is disclosed. The semiconductor device includes a gate electrode on a substrate and extending in a first direction, source/drain patterns spaced apart from each other, in a second direction, with the gate electrode interposed therebetween, a gate contact electrically connected to the gate electrode, and an active contact electrically connected to at least one of the source/drain patterns. The active contact includes a lower contact pattern electrically connected to the at least one of the source/drain patterns, the lower contact pattern having a first width in the first direction, and an upper contact pattern electrically connected to a top surface of the lower contact pattern, the upper contact pattern having a second width in the first direction that is smaller than the first width. The upper contact pattern and the gate contact horizontally overlap each other.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a gate electrode extending in a first direction; a first active pattern extending in a second direction intersecting the first direction; a second active pattern extending in the second direction and being spaced apart from the first active pattern in the first direction; a first source/drain pattern on the first active pattern and the second active pattern; a gate contact on the gate electrode, the gate contact overlapping the second active pattern in a third direction intersecting the first direction and the second direction; and an active contact on the first source/drain pattern; wherein the active contact comprises:
a lower contact pattern on the first source/drain pattern, the lower contact pattern having a first width in the first direction; and
an upper contact pattern on the lower contact pattern, the upper contact pattern having a second width in the first direction that is smaller than the first width and overlapping the first active pattern in the third direction.

2 . The semiconductor device of claim 1 ,
wherein the lower contact pattern comprises a first conductive pattern and a first barrier pattern that is on side and bottom surfaces of the first conductive pattern, and wherein the first barrier pattern is absent from at least a portion of a top surface of the first conductive pattern.

3 . The semiconductor device of claim 2 ,
wherein a top surface of the first barrier pattern is located at a level lower than a top surface of the upper contact pattern.

4 . The semiconductor device of claim 2 ,
wherein the upper contact pattern comprises a second conductive pattern and a second barrier pattern that is on side and bottom surfaces of the second conductive pattern, and wherein the second barrier pattern extends into a region between the second conductive pattern and the first conductive pattern.

5 . The semiconductor device of claim 4 ,
wherein a thickness of the second barrier pattern is different from a thickness of the first barrier pattern.

6 . The semiconductor device of claim 4 ,
wherein the second conductive pattern comprises aluminum, copper, tungsten, molybdenum, or cobalt, and wherein the first conductive pattern comprises a different one of aluminum, copper, tungsten, molybdenum, or cobalt from the second conductive pattern.

7 . The semiconductor device of claim 1 ,
wherein the upper contact pattern comprises a first side surface and a second side surface that are respectively inclined at first and second angles with respect to a top surface of the lower contact pattern, and wherein the first and second angles are acute and obtuse, respectively.

8 . The semiconductor device of claim 1 ,
wherein the upper contact pattern comprises a first side surface aligned with a side surface of the lower contact pattern.

9 . The semiconductor device of claim 1 ,
wherein the upper contact pattern comprises a first side surface and a second side surface that are respectively inclined at first and second angles with respect to a top surface of the lower contact pattern, and wherein both of the first and second angles are acute or both of the first and second angles are obtuse.

10 . The semiconductor device of claim 1 ,
wherein a bottom surface of the upper contact pattern is at a level lower than a top surface of the gate electrode.

11 . The semiconductor device of claim 1 ,
wherein a top surface of the lower contact pattern is at a level lower than a bottom surface of the gate contact, and wherein the lower contact pattern extends below a bottom surface of the gate electrode and into the first source/drain pattern.

12 . The semiconductor device of claim 1 , further comprising:
a first via on the upper contact pattern, the first via overlapping the first active pattern in the third direction; a second via on the gate contact, the second via overlapping the second active pattern in the third direction; a first interconnection line on the first via; and a second interconnection line on the second via.

13 . The semiconductor device of claim 1 ,
wherein the lower contact pattern comprises: a first end portion that is adjacent to the gate contact; and a second end portion that is opposite the first end portion in the first direction and distal from the gate contact, and wherein the upper contact pattern is on the second end portion and is absent from the first end portion.

14 . The semiconductor device of claim 1 , further comprising:
a second source/drain pattern on the first active pattern and the second active pattern and spaced apart from the first source/drain pattern in the second direction; a channel between the first source/drain pattern and the second source/drain pattern, wherein the channel comprises a plurality of channel patterns that are stacked in the third direction, and wherein the gate electrode surrounds top, bottom, and opposite side surfaces of each of the plurality of channel patterns.

15 . The semiconductor device of claim 1 , further comprising a mold pattern on the lower contact pattern and on a side surface of the upper contact pattern.

16 . The semiconductor device of claim 15 ,
wherein the mold pattern comprises a first side surface aligned with a side surface of the lower contact pattern.

17 . The semiconductor device of claim 15 ,
wherein a top surface of the mold pattern is coplanar with a top surface of the upper contact pattern.

18 . The semiconductor device of claim 17 , further comprising:
a gate capping pattern on the gate electrode; and an interlayer insulating layer on the gate capping pattern, wherein a top surface of the interlayer insulating layer is coplanar with the top surface of the mold pattern and the top surface of the upper contact pattern.

19 . The semiconductor device of claim 17 ,
wherein a first side surface of the mold pattern is contact with an interlayer insulating pattern and a second side surface of the mole pattern is contact with the side surface of the upper contact pattern.

20 . The semiconductor device of claim 15 ,
wherein a bottom surface of the mold pattern is contact with a top surface of the lower contact pattern.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Song Hyun-Seung
• Kim Tae-Yeol
• Baek Jae-Jik

Classifications

• H10W20/0693

  by forming self-aligned vias · CPC title

• H10W20/0696

  by using sacrificial placeholders, e.g. using sacrificial plugs · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/033

  in openings in dielectrics · CPC title