Semiconductor-superconductor hybrid device, its manufacture and uses

Patent metadata

Field	Value
Publication number	US-2024292761-A1
Application number	US-202418421830-A
Country	US
Kind code	A1
Filing date	Jan 24, 2024
Priority date	Oct 24, 2019
Publication date	Aug 29, 2024
Grant date	—

Abstract

A semiconductor-superconductor hybrid device comprises a semiconductor, a superconductor, and a barrier between the superconductor and the semiconductor. The device is configured to enable energy level hybridisation between the semiconductor and the superconductor. The barrier is configured to increase a topological gap of the device. The barrier allows for control over the degree of hybridisation between the semiconductor and the superconductor. Further aspects provide a quantum computer comprising the device, a method of manufacturing the device, and a method of inducing topological behaviour in the device.

First claim

1 . A semiconductor-superconductor structure, comprising:
a semiconductor nanowire having a length of at least 1 μm; a superconductor material that exhibits superconducting behavior when cooled to a temperature that induces superconducting behavior; a barrier covering a first side, a second side, and a top of the semiconductor nanowire, wherein the superconductor material is situated only on a portion of the barrier covering the first side and the top of the semiconductor nanowire, so that the barrier is situated between the superconductor material and the semiconductor nanowire, wherein the barrier is in contact with the superconductor material and the semiconductor nanowire and comprises a material of structure In 1-x A x As, wherein A is Al or Ga and x is in a range of 0.05 to 1; and a sub-composition situated in contact with a back side of the semiconductor nanowire, wherein a barrier thickness is configured to establish a topological gap.

2 . The semiconductor-superconductor structure of claim 1 , wherein at least a portion of the semiconductor nanowire has a thickness in a range of 5 to 50 nm.

3 . The semiconductor-superconductor structure of claim 1 , wherein the semiconductor nanowire comprises InAs y Sb 1-y and y is in a range of 0 to 1.

4 . The semiconductor-superconductor structure of claim 1 , wherein the semiconductor nanowire comprises InAs.

5 . The semiconductor-superconductor structure of claim 1 , wherein at least a portion of the semiconductor nanowire has a thickness in the range 10 to 40 nm.

6 . The semiconductor-superconductor structure of claim 1 , wherein A is Ga.

7 . The semiconductor-superconductor structure of claim 1 , wherein A is Al.

8 . The semiconductor-superconductor structure of claim 1 , wherein x is in the range 0.05 to 0.4.

9 . The semiconductor-superconductor structure of claim 1 , wherein x is in the range of 0.1 to 0.25.

10 . The semiconductor-superconductor structure of claim 1 , wherein the barrier has a thickness in the range 2 to 30 nm.

11 . The semiconductor-superconductor structure of claim 1 , wherein the barrier has a thickness in a range 5 to 10 nm.

12 . The semiconductor-superconductor structure of claim 1 , wherein the sub-composition includes a substrate, a barrier and a mask situated on the substrate, the barrier contacting the semiconductor nanowire and the mask contacting the superconductor material.

13 . The semiconductor-superconductor structure of claim 1 , wherein the superconductor material is aluminum.

14 . A method of manufacturing the semiconductor-superconductor structure of claim 1 , comprising:
forming a semiconductor; forming the barrier on the semiconductor; and forming the superconductor material on the barrier.

15 . The method of claim 14 , wherein forming the barrier comprises epitaxial growth of the barrier; and
wherein forming the superconductor material comprises epitaxial growth of the superconductor material.

16 . A method of inducing topological behavior in the semiconductor-superconductor structure of claim 1 , which method comprises:
cooling the semiconductor-superconductor structure to a temperature at which the superconductor material is superconductive; applying a magnetic field to the semiconductor-superconductor structure; and applying an electrostatic field to the semiconductor.

17 . The method of claim 16 , wherein the topological behavior comprises a Majorana zero mode.

18 . A semiconductor-superconductor structure, comprising:
a semiconductor material; a superconductor material that exhibits superconducting behavior when cooled to a temperature that induces superconducting behavior; and a barrier between the superconductor material and the semiconductor; wherein the barrier is configured to increase a topological gap.

19 . The semiconductor-superconductor structure of claim 18 , further comprising a ferromagnetic insulator configured to apply a magnetic field to the semiconductor and superconductor material.

20 . The semiconductor-superconductor structure of claim 19 , wherein:
the semiconductor material comprises InAs y Sb 1-y , wherein y is in a range 0 to 1 and the barrier comprises In 1-x A x As wherein A is Al or Ga and x is in a range of 0.05 to 1; and the semiconductor material is arranged between the barrier and an insulating component.

Assignees

• Microsoft Technology Licensing Llc

Inventors

• Winkler Georg Wolfgang
• Lutchyn Roman Mykolayovych
• Gardner Geoffrey Charles
• Kallaher Raymond Leonard
• Gronin Sergei Vyatcheslavovich
• Manfra Michael James
• Karimi Farhad

Classifications

• H10D62/824 Primary

  comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions · CPC title

• H10D30/402

  Single electron transistors; Coulomb blockade transistors · CPC title

• H10D64/27

  Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates · CPC title

• H10D62/121

  oriented parallel to substrates · CPC title

• H10D62/115

  Dielectric isolations, e.g. air gaps · CPC title