Semiconductor chip and component

Patent metadata

Field	Value
Publication number	US-2024275127-A1
Application number	US-202218568308-A
Country	US
Kind code	A1
Filing date	Jun 9, 2022
Priority date	Jun 11, 2021
Publication date	Aug 15, 2024
Grant date	—

Abstract

A semiconductor chip with a structured chip back side is specified, the chip back side being configured for electrical and thermal linking of the semiconductor chip, the semiconductor chip having emitter regions configured for producing electromagnetic radiation and the structured chip back side having connection pads configured for electrical linking of the emitter regions. The connection pads are p-contacts or n-contacts, with, in a plan view, all connection pads (which are configured either as p-contacts or as n-contacts overlapping with at least two of the emitter regions in each case and each of these connection pads being configured for electrical linking of only one of the emitter regions. Moreover, a component is specified, in particular comprising at least one such semiconductor chip.

First claim

1 . A semiconductor chip having a structured chip bottom side, which is configured for electrical and thermal connection of the semiconductor chip, wherein
the semiconductor chip comprises emitter regions configured for generating electromagnetic radiation, the structured chip bottom side comprises connection pads configured for the electrical connection of the emitter regions and the connection pads are p-contacts or n-contacts and in top view, either all connection pads formed as p-contacts or all connection pads formed as n-contacts overlap in each case with at least two of the emitter regions and are each configured for the electrical connection of only one of the emitter regions

2 . The semiconductor chip according to claim 1 comprising a chip top side and a lateral surface, wherein
the lateral surface connects the chip top side to the chip bottom side,
the semiconductor chip is formed as an edge-emitting semiconductor chip, and
during operation of the semiconductor chip, electromagnetic radiation is coupled out from the semiconductor chip at the lateral surface.

3 . The semiconductor chip according to claim 1 , wherein in top view, all connection pads, which are formed either as p-contacts or as n-contacts, overlap in each case with three, four or with all emitter regions of the semiconductor chip.

4 . The semiconductor chip according to claim 1 , wherein the connection pads are p-contacts, and in addition to the connection pads formed as p-contacts, the semiconductor chip has further connection pads, wherein the further connection pads form n-contacts of the semiconductor chip, and the p-contacts and n-contacts of the semiconductor chip are located on a common contacting plane.

5 . The semiconductor chip according to claim 1 , which comprises a semiconductor body with the emitter regions, an electrical distribution layer and an insulating layer, wherein
the insulating layer is arranged in vertical direction between the semiconductor body and the connection pads, the insulating layer has at least one opening, in which an electrically conductive through-contact is formed, and one of the connection pads is electrically conductively connected to the electrical distribution layer via the through-contact.

6 . The semiconductor chip according to claim 5 , wherein a plurality of through-contacts are arranged in the insulating layer, and wherein the electrical distribution layer is electrically conductively connected to a plurality of connection pads via the plurality of through-contacts.

7 . The semiconductor chip according to claim 5 , wherein the insulating layer forms a single insulating plane of the semiconductor chip between the electrical distribution layer and the chip bottom side.

8 . The semiconductor chip according to 5 comprising a plurality of connection pads and through-contacts, wherein
the connection pads are each configured to make electrical contact with one single emitter region, and
in top view, the connection pads each overlap with at least two or with several emitter regions.

9 . The semiconductor chip according to claim 1 , which, in addition to the connection pads, comprises further connection pads, wherein the connection pads and the further connection pads form p-contacts and n-contacts of the semiconductor chip, and wherein the p-contacts and the n-contacts of the semiconductor chip are located on a common contacting plane.

10 . The semiconductor chip according to claim 1 , wherein the emitter regions of the semiconductor chip run parallel to one another and are each formed as a ridge region, the emitter regions being configured for generating coherent electromagnetic radiation.

11 . The semiconductor chip according to claim 1 , wherein the structured chip bottom side with the connection pads is formed in a honeycombed or matrix-like manner.

12 . A component ( 100 ) having at least one semiconductor chip according to claim 1 and a carrier, wherein the at least one semiconductor chip is arranged on the carrier and is electrically conductively connected to the carrier via a structured contact structure of the carrier.

13 . The component according to claim 12 , wherein
the semiconductor chip has a semiconductor body, the semiconductor body being electrically conductively connected to contact pads on the carrier via an electrical distribution layer and via the connection pads on the chip bottom side, the electrical distribution layer is arranged between the semiconductor body and the carrier, and a single insulating layer is arranged between the electrical distribution layer and the carrier.

14 . The component according to claim 12 comprising a plurality of emitter regions, a plurality of connection pads, and a plurality of through-contacts, wherein
the connection pads are each configured to make electrical contact with one single emitter region, and
in top view, the connection pads each overlap with at least two or with several emitter regions.

15 . The component according to claims 12 comprising a plurality of emitter regions, a plurality of connection pads, and a plurality of through-contacts, wherein
the emitter regions are each electrically conductively connected to contact pads of the structured contact structure of the carrier via a plurality of connection pads and a plurality of through-contacts, and
the connection pads are each assigned to at most one single emitter region of the emitter regions.

16 . The component according to claim 12 , wherein the chip bottom side of the semiconductor chip and/or the structured contact structure of the carrier are/is formed in a honeycombed or matrix-like manner.

17 . The component according to claim 12 comprising a further semiconductor chip which is arranged next to the semiconductor chip on the carrier and is electrically conductively connected to the carrier via the structured contact structure of the carrier, wherein
the semiconductor chips are different from a single-emitter and each have at least two emitter regions,
the semiconductor chips each have a chip bottom side with at least two connection pads, and
the at least two connection pads are configured for making electrical contact with one single emitter region and, in top view, each overlap with at least two emitter regions.

18 . The component according to claim 17 , comprising a plurality of resonators, wherein the semiconductor chips and the emitter regions are arranged next to each other that during operation of the component, spectra of individual emitter regions are superimposed with a wavelength offset which is from 2 μm to 5 μm between the individual resonators, thereby achieving a spectral width of 10 nm +/−5 nm.

19 . A semiconductor chip having a structured chip bottom side which is configured for electrical and thermal connection of the semiconductor chip, wherein
the semiconductor chip comprises emitter regions configured for generating electromagnetic radiation, the structured chip bottom side comprises connection pads configured for the electrical connection of the emitter regions, and the connection pads are p-contacts or n-contacts and in top view, either all connection pads formed as p-contacts or all connection pads formed as n-contacts overlap in each case with all emitter regions of the semiconductor chip and are each configured for the electrical connection of only one of the emitter regions.

20 . A semiconductor chip having a structured chip bottom side which is configured for electrical and thermal connection of

Assignees

• Ams Osram Int Gmbh

Inventors

• Sorg Jörg Erich
• Heinemann Erik
• Somers André
• Kippes Thomas
• Schlegl Sebastian
• Heidemann Matthias

Classifications

• H01S5/22

  having a ridge or stripe structure · CPC title

• H01S5/02315

  Support members, e.g. bases or carriers · CPC title

• H01S5/0234

  Up-side down mountings, e.g. Flip-chip, epi-side down mountings or junction down mountings · CPC title

• H01S5/4031

  Edge-emitting structures · CPC title

• H01S5/04257 Primary

  having positive and negative electrodes on the same side of the substrate · CPC title