Voltage generation circuit and semiconductor memory device including the same

Patent metadata

Field	Value
Publication number	US-2024274212-A1
Application number	US-202318241621-A
Country	US
Kind code	A1
Filing date	Sep 1, 2023
Priority date	Feb 15, 2023
Publication date	Aug 15, 2024
Grant date	—

Abstract

A voltage generation circuit includes a current generation circuit, a slope trimming circuit and an offset trimming circuit. The current generation circuit is connected between an input voltage node and an output node that outputs a complementary to absolute temperature (CTAT) output voltage that decreases as an operation temperature increases. The current generation circuit generates a reference current flowing through the output node, the reference current having a constant magnitude regardless of the operation temperature. The slope trimming circuit is connected between the output node and an intermediate node. The slope trimming circuit adjusts a slope of the CTAT output voltage based on a first trimming code. The offset trimming circuit is connected between the intermediate node and a ground voltage node. The offset trimming circuit configured to adjust an offset voltage of the CTAT output voltage based on a second trimming code.

First claim

What is claimed is:

1 . A voltage generation circuit comprising:
a current generation circuit connected between an input voltage node and an output node that outputs a complementary to absolute temperature (CTAT) output voltage that decreases as an operation temperature increases, the current generation circuit configured to generate a reference current flowing through the output node, the reference current having a constant magnitude regardless of the operation temperature; a slope trimming circuit connected between the output node and an intermediate node, the slope trimming circuit configured to adjust a slope of the CTAT output voltage based on a first trimming code; and an offset trimming circuit connected between the intermediate node and a ground voltage node, the offset trimming circuit configured to adjust an offset voltage of the CTAT output voltage based on a second trimming code.

2 . The voltage generation circuit of claim 1 , wherein the offset voltage has a constant magnitude regardless of the operation temperature.

3 . The voltage generation circuit of claim 1 , wherein the current generation circuit includes:
a first bias voltage generation circuit configured to generate a first bias voltage that increases as the operation temperature increases; a second bias voltage generation circuit configured to generate a second bias voltage that decreases as the operation temperature increases; a first current source connected between the input voltage node and the output node, the first current source configured to generate a first current based on the first bias voltage, the first current increasing as the operation temperature increases; and a second current source connected in parallel to the first current source between the input voltage node and the output node, the second current source configured to generate a second current based on the second bias voltage, the second current decreasing as the operation temperature increases.

4 . The voltage generation circuit of claim 3 , wherein the first current source includes:
a first P-type metal oxide semiconductor (PMOS) transistor including a gate electrode that receives the first bias voltage, a source electrode connected to the input voltage node and a drain electrode connected to the output node, and wherein the second current source includes: a second PMOS transistor including a gate electrode that receives the second bias voltage, a source electrode connected to the input voltage node and a drain electrode connected to the output node.

5 . The voltage generation circuit of claim 1 , wherein the slope trimming circuit includes:
a plurality of diode-connected transistors connected in parallel between the output node and the intermediate node; and a plurality of switches connected between the output node and respective ones of the plurality of diode-connected transistors and being turned on based on respective bits of the first trimming code.

6 . The voltage generation circuit of claim 5 , wherein the plurality of diode-connected transistors are implemented with PMOS transistors, and at least two of the PMOS transistors have sizes different from each other.

7 . The voltage generation circuit of claim 1 , wherein the offset trimming circuit includes:
a plurality of resistors connected in series between the intermediate node and the ground voltage node; and a plurality of switches connected in parallel with respective ones of the plurality of resistors and being turned on based on respective bits of the second trimming code.

8 . The voltage generation circuit of claim 7 , wherein at least two of the plurality of resistors have resistance values different from each other.

9 . A semiconductor memory device comprising:
a memory cell array including a plurality of memory cells respectively connected to a plurality of wordlines and a plurality of bitlines; and a voltage generator including a voltage generation circuit, the voltage generator configured to output voltages to drive the plurality of wordlines, the voltages being based on a complementary to absolute temperature (CTAT) output voltage that decreases as an operation temperature increases, wherein the voltage generation circuit includes:
a current generation circuit connected between an input voltage node and an output node that outputs the CTAT output voltage, the current generation circuit configured to generate a reference current flowing through the output node, the reference current having a constant magnitude regardless of the operation temperature;
a slope trimming circuit connected between the output node and an intermediate node, the slope trimming circuit configured to adjust a slope of the CTAT output voltage based on a first trimming code; and
an offset trimming circuit connected between the intermediate node and a ground voltage node, the offset trimming circuit configured to adjust an offset voltage of the CTAT output voltage based on a second trimming code.

10 . The semiconductor memory device of claim 9 , wherein the semiconductor memory device is a NAND flash memory device.

11 . The semiconductor memory device of claim 10 , wherein the voltage generator is configured to generate, using the voltage generation circuit, a read voltage and a read pass voltage that are output to the plurality of wordlines during a read operation.

12 . The semiconductor memory device of claim 10 , wherein the voltage generator is configured to generate, using the voltage generation circuit, a program voltage and a program pass voltage that are output to the plurality of wordlines during a program operation.

13 . The semiconductor memory device of claim 10 , wherein the voltage generator is configured to generate, using the voltage generation circuit, a precharge voltage that is output to the plurality of bitlines during a read operation.

14 . The semiconductor memory device of claim 9 , wherein the semiconductor memory device is a dynamic random access memory (DRAM) device.

15 . The semiconductor memory device of claim 14 , wherein the voltage generator is configured to generate, using the voltage generation circuit, a selection wordline voltage that is output to a selected wordline of the plurality of wordlines during a write operation and a read operation.

16 . The semiconductor memory device of claim 14 , wherein the voltage generator is configured to generate, using the voltage generation circuit, a bitline voltage that is output to the plurality of bitlines during a read operation.

17 . The semiconductor memory device of claim 9 , further comprising:
a nonvolatile code storage configured to store the first trimming code and the second trimming code.

18 . The semiconductor memory device of claim 17 , wherein the first trimming code and the second trimming code are generated during a test process of the semiconductor memory device and stored in the nonvolatile code storage.

19 . The semiconductor memory device of claim 9 , wherein the offset voltage has a constant magnitude regardless of the operation temperature of the semiconductor memory device.

20 . A voltage generation circuit comprising:
a first bias voltage generation circuit configured to generate a first bias voltage that increases as an operation temperature increases; a second bias voltage generation circuit configured to generate a second bias voltage that decreases as the operation temperature increases; a first current source connected between an input voltage node and an output nod

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Yumin
• Lee Jungyu
• Park Jihyun
• Yoon Chiweon
• Lee Eunchan

Classifications

• G11C7/12 Primary

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title

• G11C29/50012

  of timing · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title

• G11C29/021

  in voltage or current generators · CPC title

• G11C16/24

  Bit-line control circuits · CPC title