System and Method for Power Module Defect Detection

Patent metadata

Field	Value
Publication number	US-2024272088-A1
Application number	US-202318168017-A
Country	US
Kind code	A1
Filing date	Feb 13, 2023
Priority date	Feb 13, 2023
Publication date	Aug 15, 2024
Grant date	—

Abstract

In an embodiment, a method includes: capturing a first image of a power module, the power module including a power electronics circuit, the power electronics circuit including power semiconductor dies; identifying positions of the power semiconductor dies in the first image with a die detection model; extracting second images of the power semiconductor dies from the first image according to the positions of the power semiconductor dies in the first image; and identifying defects of the power semiconductor dies in the second images with a defect detection model, the defect detection model being different from the die detection model.

First claim

What is claimed is:

1 . A system comprising:
a processing tool configured to perform a manufacturing process to form a power module, the power module comprising power semiconductor dies; a camera configured to capture a first image of the power module; and a controller configured to:
identify positions of the power semiconductor dies in the first image with a die detection model;
extract second images of the power semiconductor dies from the first image according to the positions of the power semiconductor dies; and
identify defects in the second images with a defect detection model, the defect detection model being different from the die detection model.

2 . The system of claim 1 , wherein the controller is further configured to:
control the processing tool to stop the manufacturing process in response to identifying the defects in the second images.

3 . The system of claim 1 , wherein the camera comprises an optical microscope configured to sense ultraviolet light rays, and the power module further comprises a passivation layer on the power semiconductor dies, the passivation layer being transparent to the ultraviolet light rays.

4 . The system of claim 1 , wherein the die detection model comprises a convolutional neural network, and the controller is configured to identify the positions of the power semiconductor dies in the first image by processing the first image with the convolutional neural network to simultaneously predict bounding boxes of the power semiconductor dies in the first image and predict class probabilities for the bounding boxes.

5 . The system of claim 4 , wherein the controller is further configured to identify the positions of the power semiconductor dies in the first image by downsizing the first image before processing the first image with the convolutional neural network.

6 . The system of claim 1 , wherein the defect detection model comprises a convolutional neural network, and the controller is configured to identify the defects of the power semiconductor dies in the second images by processing the second images with the convolutional neural network to simultaneously predict bounding boxes of the defects in the second images and predict class probabilities for the bounding boxes.

7 . The system of claim 6 , wherein the controller is further configured to identify the defects of the power semiconductor dies by upsizing the second images before processing the second images with the convolutional neural network.

8 . The system of claim 1 , wherein the controller comprises a memory, and the die detection model and the defect detection model are stored in the memory.

9 . A method comprising:
capturing a first image of a power module, the power module comprising a power electronics circuit, the power electronics circuit comprising power semiconductor dies; identifying positions of the power semiconductor dies in the first image with a die detection model; extracting second images of the power semiconductor dies from the first image according to the positions of the power semiconductor dies in the first image; and identifying defects of the power semiconductor dies in the second images with a defect detection model, the defect detection model being different from the die detection model.

10 . The method of claim 9 , wherein the power electronics circuit further comprises a gate driver and passive devices.

11 . The method of claim 9 , wherein the power electronics circuit is a chopper circuit, a DC-to-DC converter circuit, an inverter circuit, or a relay circuit.

12 . The method of claim 9 , wherein the power semiconductor dies are silicon carbide dies.

13 . The method of claim 9 , wherein capturing the first image comprises sensing ultraviolet light rays with an optical microscope, and the power module further comprises a passivation layer on the power semiconductor dies, the passivation layer being transparent to the ultraviolet light rays.

14 . The method of claim 9 , wherein the die detection model comprises a convolutional neural network, and identifying the positions of the power semiconductor dies in the first image comprises processing the first image with the convolutional neural network to simultaneously predict bounding boxes of the power semiconductor dies in the first image and predict class probabilities for the bounding boxes.

15 . The method of claim 14 , wherein identifying the positions of the power semiconductor dies in the first image further comprises downsizing the first image before processing the first image with the convolutional neural network.

16 . The method of claim 9 , wherein the defect detection model comprises a convolutional neural network, and identifying the defects of the power semiconductor dies in the second images comprises processing the second images with the convolutional neural network to simultaneously predict bounding boxes of the defects in the second images and predict class probabilities for the bounding boxes.

17 . The method of claim 16 , wherein identifying the defects of the power semiconductor dies further comprises upsizing the second images before processing the second images with the convolutional neural network.

18 . The method of claim 9 further comprising:
training the die detection model with power module images; and
training the defect detection model with power semiconductor die images.

19 . The method of claim 9 further comprising:
performing a manufacturing process to form the power module, the defects of the power semiconductor dies being from the manufacturing process; and
stopping the manufacturing process in response to identifying the defects of the power semiconductor dies.

20 . The method of claim 9 further comprising:
performing a testing process to test the power module, the defects of the power semiconductor dies being from the testing process; and
confirming the defects of the power semiconductor dies are present by visual inspection.

21 . A method comprising:
training a defect detection model with first images of first power semiconductor dies, the defect detection model comprising a convolutional neural network; forming a power module comprising second power semiconductor dies; capturing second images of the second power semiconductor dies; and identifying defects of the second power semiconductor dies in the second images with the defect detection model by processing the second images with the convolutional neural network to simultaneously predict bounding boxes of the defects in the second images and predict class probabilities for the bounding boxes.

Assignees

• St Microelectronics Srl

Inventors

• Calabretta Michele
• Rundo Francesco
• Coffa Salvatore
• Torrisi Marco Alfio
• Sarpietro Riccardo Emanuele

Classifications

• G06T2207/20084

  Artificial neural networks [ANN] · CPC title

• G06T2207/20081

  Training; Learning · CPC title

• G06T2207/30148

  Semiconductor; IC; Wafer · CPC title

• G01N2021/8887

  based on image processing techniques · CPC title

• G01N2021/8883

  involving the calculation of gauges, generating models · CPC title