Current-to-voltage converter comprising common mode circuit

Patent metadata

Field	Value
Publication number	US-2024265951-A1
Application number	US-202318137370-A
Country	US
Kind code	A1
Filing date	Apr 20, 2023
Priority date	Feb 2, 2023
Publication date	Aug 8, 2024
Grant date	—

Abstract

In one example, a system comprises a current-to-voltage converter to generate differential voltages from differential currents comprising a first current and a second current, the current-to-voltage converter comprising: a first bitline to provide the first current; a second bitline to provide the second current; a first regulator to apply a first voltage to the first bitline; a second regulator to apply a second voltage to the second bitline; a regulating circuit comprising a first input terminal, a second input terminal, a first output terminal, and a second output terminal, the first output terminal and the second output terminal providing the differential voltages; and a common mode circuit.

First claim

What is claimed is:

1 . A system comprising:
a current-to-voltage converter to generate differential voltages from differential currents comprising a first current and a second current, the current-to-voltage converter comprising:
a first bitline to provide the first current;
a second bitline to provide the second current;
a first regulator to apply a first voltage to the first bitline;
a second regulator to apply a second voltage to the second bitline;
a regulating circuit comprising a first input terminal, a second input terminal, a first output terminal, and a second output terminal, the first output terminal and the second output terminal providing the differential voltages; and
a common mode circuit comprising a first terminal coupled to the first bitline and the first input terminal of the regulating circuit and a second terminal coupled to the second bitline and the second input terminal of the regulating circuit, wherein the common mode circuit maintains a same voltage on the first terminal and the second terminal.

2 . The system of claim 1 comprising:
an analog-to-digital converter to convert the generated differential voltages into a digital output.

3 . The system of claim 1 , wherein the regulating circuit is an operational amplifier.

4 . The system of claim 3 , comprising:
a first resistor coupled between the first input terminal of the operational amplifier and the first output terminal of the operational amplifier; and a second resistor coupled between the second input terminal of the operational amplifier and the second output terminal of the operational amplifier.

5 . The system of claim 4 , wherein the first resistor is a fixed resistor and the second resistor is a fixed resistor.

6 . The system of claim 4 , wherein the first resistor is a first variable resistor and the second resistor is a second variable resistor.

7 . The system of claim 4 , comprising:
a first capacitor coupled between the first input terminal of the operational amplifier and the first output terminal of the operational amplifier; and a second capacitor coupled between the second input terminal of the operational amplifier and the second output terminal of the operational amplifier.

8 . The system of claim 7 , wherein the first capacitor is a first fixed capacitor and the second capacitor is a second fixed capacitor.

9 . The system of claim 7 , wherein the first capacitor is a first variable capacitor and the second capacitor is a second variable capacitor.

10 . The system of claim 3 , comprising:
a first capacitor coupled between the first input terminal of the operational amplifier and the first output terminal of the operational amplifier; and a second capacitor coupled between the second input terminal of the operational amplifier and the second output terminal of the operational amplifier.

11 . The system of claim 10 , wherein the first capacitor is a first fixed capacitor and the second capacitor is a second fixed capacitor.

12 . The system of claim 10 , wherein the first capacitor is a first variable capacitor and the second capacitor is a second variable capacitor.

13 . The system of claim 1 , wherein the common mode circuit comprises a first current source to receive a bias voltage and a second current source to receive the bias voltage.

14 . The system of claim 1 , wherein the common mode circuit comprises a first variable resistor and a second variable resistor, the first variable resistor and the second variable resistor to receive a bias voltage.

15 . The system of claim 1 , wherein the common mode circuit comprises a first PMOS transistor and a second PMOS transistor, the first PMOS transistor and the second PMOS transistor to receive a bias voltage.

16 . The system of claim 1 , wherein the common mode circuit comprises a first NMOS transistor and a second NMOS transistor, the first NMOS transistor and the second NMOS transistor to receive a bias voltage.

17 . The system of claim 1 , wherein the common mode circuit comprises a first capacitor and a second capacitor, the first capacitor and the second capacitor to receive a bias voltage.

18 . A system comprising:
a bitline regulation circuit comprising:
a first set of switches coupled to a bitline; and
a second set of switches coupled to the bitline;
wherein the bitline regulation circuit receives a first input from the first set of switches and a second input from the second set of switches, the first input comprising voltage and current and the second input comprising voltage and no current.

19 . The system of claim 18 , wherein the bitline regulation circuit comprises an enhancement mode NMOS transistor.

20 . The system of claim 18 , wherein the bitline regulation circuit comprises a native NMOS transistor.

21 . The system of claim 18 , wherein the bitline regulation circuit comprises an enhancement mode NMOS transistor, a native NMOS transistor, and a PMOS transistor that are used to receive different ranges of the current from the bitline.

22 . The system of claim 18 , wherein the system comprises a current-to-voltage converter and the bitline regulation circuit is part of the current-to-voltage converter.

23 . The system of claim 22 , comprising an analog-to-digital converter.

24 . The system of claim 22 , comprising a neural memory array.

25 . The system of claim 24 , wherein the bitline regulation circuit is used during a verify operation of the neural memory array using the first input or the second input.

26 . A system comprising:
an array of memory cells arranged in rows and columns, the array comprising bitlines coupled to respective columns in the array, respective bitlines comprising a sensing bitline metal layer and a current-carrying metal layer, wherein the sensing bitline metal layer does not carry current.

27 . The system of claim 26 , comprising a bitline regulation circuit coupled to the sensing bitline metal layer and the current-carrying metal later.

28 . The system of claim 27 , comprising an analog-to-digital converter.

29 . A system comprising:
an output block comprising:
a first regulator comprising a first operational amplifier and a first set of switches coupled to a first bitline to receive a W+ value;
a second regulator comprising a second operational amplifier and a second set of switches coupled to a second bit line, the second regulator to receive a W− value, where a weight W=W+−W−; and
a regulating circuit to receive a first input from the first regulator and a second input from the second regulator and comprising one or more of a feedback resistor and a feedback capacitor;
wherein the first regulator provides the first input to the regulating circuit during a verification operation of one or more memory cells coupled to the first bitline and the second regulator provides the second input to the regulating circuit during a verification operation of one or more memory cells coupled to the second bitline; and
wherein the first regulator provides the first input to the regulating circuit and the second regulator provides the second input to the regulating circuit during read neural operation.

30 . The system of claim 29 , wherein, during a verification operation of one or more memory cells coupled to the first bitline, the first operationa

Assignees

• Silicon Storage Tech Inc

Inventors

• Tran Hieu Van
• Vu Hoa
• Trinh Stephen
• Hong Stanley
• Vu Thuan
• Le Nghia
• Nguyen Duc
• Pham Hien

Classifications

• G11C5/147 Primary

  Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence) · CPC title

• G11C7/02

  with means for avoiding parasitic signals · CPC title

• G11C11/54

  using elements simulating biological cells, e.g. neuron · CPC title

• G11C16/24

  Bit-line control circuits · CPC title

• G11C13/004 Primary

  Reading or sensing circuits or methods · CPC title