Array base plate, display panel and display device

Patent metadata

Field	Value
Publication number	US-2024265861-A1
Application number	US-202218021438-A
Country	US
Kind code	A1
Filing date	Jun 29, 2022
Priority date	Jun 29, 2022
Publication date	Aug 8, 2024
Grant date	—

Abstract

An array base plate includes a silicon substrate including multiple cascaded EOA units disposed at a peripheral area; the EOA units are electrically connected to a pixel driving unit; each EOA unit includes an input circuit transmitting a signal input by a light-emitting control signal input line to the EOA unit; a first control circuit transmitting a second power signal input by a second power signal line to a first node, and transmitting a first power signal input by a first power signal line to a second node; a second control circuit transmitting a second clock signal to a third node or transmitting the second power signal to the third node; a pull-up circuit transmitting the first power signal to a light-emitting control signal output line, and a pull-down circuit transmitting the second power signal to the light-emitting control signal output line.

First claim

1 . An array base plate, comprising:
a silicon substrate, wherein the silicon substrate comprises a display area and a peripheral area located on at least one side of the display area, a plurality of EOA units that are cascaded and disposed at the peripheral area, and a plurality of sub-pixels disposed at the display area; at least one of the plurality of sub-pixels comprises a pixel driving unit, the EOA units are electrically connected to the pixel driving unit, and each of the plurality of EOA units comprises: an input circuit, wherein the input circuit is electrically connected to a light-emitting control signal input line and a first clock signal line, and the input circuit is configured to transmit a signal input by the light-emitting control signal input line to the EOA unit under the control of the first clock signal input by the first clock signal line; a first control circuit, wherein the first control circuit is electrically connected to the input circuit, the first clock signal line, a second clock signal line, a first node, a second node, a first power signal line and a second power signal line, the first control circuit is configured to transmit a second power signal input by the second power signal line to the first node under the control of the first clock signal, and is further configured to transmit a first power signal input by the first power signal line to the second node under the joint control of a signal of the first node and a second clock signal input by the second clock signal line; a second control circuit, wherein the second control circuit is electrically connected to the first power signal line, the first node, the second node, the second clock signal line and a third node, the second control circuit is configured to transmit the second clock signal to the third node under the joint control of a signal of the first node and the second clock signal; the second control circuit is further configured to transmit the second power signal to the third node under the control of a signal of the second node; a pull-up circuit, wherein the pull-up circuit is electrically connected to the first control circuit, the second control circuit, a light-emitting control signal output line and the third node, and the pull-up circuit is configured to transmit the first power signal to the light-emitting control signal output line under the control of a signal of the third node; and a pull-down circuit, wherein the pull-down circuit is electrically connected to the first control circuit, the second control circuit, the second clock signal line, the light-emitting control signal output line and the second node, and the pull-down circuit is configured to transmit the second power signal to the light-emitting control signal output line under the control of the signal of the second node.

2 . The array base plate according to claim 1 , wherein the input circuit comprises a first transistor, the first control circuit comprises a second transistor, a third transistor, a fourth transistor and a fifth transistor:
a gate of the first transistor is electrically connected to the first clock signal line, a first pole of the first transistor is electrically connected to the second node, a second pole of the first transistor is electrically connected to the light-emitting control signal input line; a gate of the second transistor is electrically connected to the second node, a first pole of the second transistor is electrically connected to the first clock signal line, a second pole of the second transistor is electrically connected to the first node; a gate of the third transistor is electrically connected to the first clock signal line, a first pole of the third transistor is electrically connected to the first node, a second pole of the third transistor is electrically connected to the second power signal line; a gate of the fourth transistor is electrically connected to the first node, a first pole of the fourth transistor is electrically connected to the first power signal line, a second pole of the fourth transistor is electrically connected to a first pole of the fifth transistor; and a gate of the fifth transistor is electrically connected to the second clock signal line, a second pole of the fifth transistor is electrically connected to the second node.

3 . The array base plate according to claim 2 , wherein the second control circuit comprises a sixth transistor, a seventh transistor, an eighth transistor and a first capacitor;
a gate of the sixth transistor is electrically connected to the second node, a first pole of the sixth transistor is electrically connected to the first power signal line, a second pole of the sixth transistor is electrically connected to the third node; a gate of the seventh transistor is electrically connected to the second clock signal line, a first pole of the seventh transistor is electrically connected to the third node, a second pole of the seventh transistor is electrically connected to a first pole of the eighth transistor; a gate of the eighth transistor is electrically connected to the first node, a second pole of the eighth transistor is electrically connected to the second clock signal line; and a first electrode of the first capacitor is electrically connected to the first pole of the eighth transistor, a second electrode of the first capacitor is electrically connected to the gate of the eighth transistor.

4 . The array base plate according to claim 3 , wherein the pull-up circuit comprises a ninth transistor and a third capacitor, the pull-down circuit comprises a tenth transistor and a second capacitor:
a gate of the ninth transistor is electrically connected to the third node, a first pole of the ninth transistor is electrically connected to the first power signal line, a second pole of the ninth transistor is electrically connected to the light-emitting control signal output line; a first electrode of the third capacitor is electrically connected to the first pole of the ninth transistor, a second electrode of the third capacitor is electrically connected to the gate of the ninth transistor; and a gate of the tenth transistor is electrically connected to the second node, a first pole of the tenth transistor is electrically connected to the light-emitting control signal output line, a second pole of the tenth transistor electrically connected to the second power signal line; a first electrode of the second capacitor is electrically connected to the gate of the tenth transistor, a second electrode of the second capacitor is electrically connected to the second clock signal line.

5 . The array base plate according to claim 4 , wherein each of the plurality of EOA units further comprises a forward scan transistor and a reverse sweep transistor; the array base plate further comprises a forward scan control signal line and a reverse sweep control signal line, a gate of the forward scan transistor is electrically connected to the forward scan control signal line, a gate of the reverse sweep transistor is electrically connected to the reverse sweep control signal line;
a first pole of the forward scan transistor of the EOA unit at a n-th level is electrically connected to the second pole of the first transistor of the EOA unit at a (n+1)-th level, a second pole of the forward scan transistor of the EOA unit at the n-th level is electrically connected to the forward scan signal output line of the EOA unit at the n-th level; and a first pole of the reverse sweep transistor of the EOA unit at the n-th level is electrically connected to the reverse sweep signal output line of the EOA unit at the (n+1)-th level, a second pole of the reverse sweep transistor of the EOA unit at the n-th level is electrically connected to the second pole of the first transistor of the EOA unit at the n-t

Assignees

• Yunnan Invensight Optoelectronics Technology Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Ma Yaoxi
• Fan Longfei
• Lu Pengcheng
• Yang Shengji
• Chen Xiaochuan
• Jiang Shanghong
• Zhu Zhijian
• Fan Huaiyun

Classifications

• G09G3/3233

  with pixel circuitry controlling the current through the light-emitting element · CPC title

• G11C19/287

  Organisation of a multiplicity of shift registers · CPC title

• G09G3/3266

  Details of drivers for scan electrodes · CPC title

• G09G3/3225 Primary

  using an active matrix · CPC title

• H10K59/131 Primary

  Interconnections, e.g. wiring lines or terminals · CPC title