Comparator and image sensor including the same

Patent metadata

Field	Value
Publication number	US-2024259713-A1
Application number	US-202418407717-A
Country	US
Kind code	A1
Filing date	Jan 9, 2024
Priority date	Feb 1, 2023
Publication date	Aug 1, 2024
Grant date	—

Abstract

Provided are a comparator and an image sensor including the same. The comparator includes a first input transistor including a gate connected to a first input node, a second input transistor including a gate connected to a second input node, a first load transistor including a drain connected to the first input transistor, a second load transistor including a drain connected to the second input transistor, a first shift transistor including a drain connected to the first load transistor, a second shift transistor including a drain connected to the second load transistor, a first bottom switch connected to the first load transistor in parallel, a second bottom switch connected to the second load transistor in parallel, a first top switch connected to the first shift transistor in parallel, and a second top switch connected to the second shift transistor in parallel.

First claim

1 . A comparator comprising:
a first input transistor comprising a gate connected to a first input node; a second input transistor comprising a gate connected to a second input node; a first load transistor comprising a drain connected to a drain of the first input transistor; a second load transistor comprising a drain connected to a drain of the second input transistor; a first shift transistor comprising a drain connected to a source of the first load transistor; a second shift transistor comprising a drain connected to a source of the second load transistor; a first bottom switch connected to the first load transistor in parallel; a second bottom switch connected to the second load transistor in parallel; a first top switch connected to the first shift transistor in parallel; and a second top switch connected to the second shift transistor in parallel.

2 . The comparator of claim 1 , further comprising:
a first auto-zero switch that is operable to connect the first input node to the drain of the first input transistor; and a second auto-zero switch that is operable to connect the second input node to the drain of the second input transistor.

3 . The comparator of claim 1 , wherein a threshold voltage of the first shift transistor is higher than a threshold voltage of the first load transistor.

4 . The comparator of claim 1 , wherein the comparator is configured to operate in a first auto-zero period, a first comparison period, a second auto-zero period, and a second comparison period, and
wherein, in the first auto-zero period, the first comparison period, and the second comparison period, the first top switch and the second top switch are turned on, and the first bottom switch and the second bottom switch are turned off.

5 . The comparator of claim 1 , wherein the comparator is configured to operate in a first auto-zero period, a first comparison period, a second auto-zero period, and a second comparison period, and
wherein, in the second auto-zero period, the first top switch and the second top switch are turned off, and the first bottom switch and the second bottom switch are turned on.

6 . The comparator of claim 1 , wherein the comparator is configured to operate in a first auto-zero period, a first comparison period, a second auto-zero period, and a second comparison period, and
the first top switch, the second top switch, the first bottom switch, and the second bottom switch are turned on in a period other than the first auto-zero period, the first comparison period, the second auto-zero period, and the second comparison period.

7 .- 8 . (canceled)

9 . An image sensor comprising:
a pixel array comprising a plurality of pixels; a ramp generator configured to generate a ramp signal; and an analog-digital conversion circuit configured to convert a pixel signal, which is output from the pixel array, into a digital signal, the analog-digital conversion circuit comprising a comparator and a counter, wherein the comparator comprises: a first input transistor comprising a gate configured to receive the ramp signal; a second input transistor comprising a gate configured to receive the pixel signal; a first load transistor connected to a source or drain of the first input transistor; a second load transistor connected to a source or drain of the second input transistor; a first shift transistor comprising a gate connected to the gate of the first input transistor and connected to a source or drain of the first load transistor; and a second shift transistor comprising a gate connected to the gate of the second input transistor and connected to a source or drain of the second load transistor, the first load transistor and the first shift transistor are configured to be selectively driven according to a first switching signal and a second switching signal, respectively, and the second load transistor and the second shift transistor are configured to be selectively driven according to the first switching signal and the second switching signal, respectively.

10 . The image sensor of claim 9 , wherein the source of the first load transistor is connected to the drain of the first shift transistor, and
the source of the second load transistor is connected to the drain of the second shift transistor.

11 . The image sensor of claim 10 , wherein the comparator comprises:
a first bottom switch connected to the first load transistor in parallel and configured to be switched between open and closed states according to the first switching signal; a second bottom switch connected to the second load transistor in parallel and configured to be switched between open and closed states according to the first switching signal; a first top switch connected to the first shift transistor in parallel and configured to be switched between open and closed states according to the second switching signal; and a second top switch connected to the second shift transistor in parallel and configured to be switched between open and closed states according to the second switching signal.

12 . The image sensor of claim 9 , wherein the drain of the first load transistor is connected to the drain of the first shift transistor, and
the drain of the second load transistor is connected to the drain of the second shift transistor.

13 . The image sensor of claim 12 , wherein the comparator comprises:
a first bottom switch connected to the first shift transistor in series and configured to be switched between open and closed states according to the first switching signal; a second bottom switch connected to the second shift transistor in series and configured to be switched between open and closed states according to the first switching signal; a first top switch connected to the first load transistor in series and configured to be switched between open and closed states according to the second switching signal; and a second top switch connected to the second load transistor in series and configured to be switched between open and closed states according to the second switching signal.

14 . The image sensor of claim 12 , wherein the comparator further comprises a pull-up switch configured to apply a power voltage to the source or drain of the first input transistor and the source or drain of the second input transistor.

15 . The image sensor of claim 9 , wherein the comparator further comprises:
a first auto-zero switch that is operable to connect the gate of the first input transistor to the source or drain of the first input transistor; and a second auto-zero switch that is operable to connect the gate of the second input transistor to the source or drain of the second input transistor.

16 . The image sensor of claim 9 , wherein a threshold voltage of the first shift transistor is higher than a threshold voltage of the first load transistor.

17 . The image sensor of claim 9 , wherein the comparator is configured to operate in a first auto-zero period, a first comparison period, a second auto-zero period, and a second comparison period,
wherein, in the first auto-zero period, the first load transistor and the second load transistor are driven, and wherein, in the second auto-zero period, the first shift transistor and the second shift transistor are driven.

18 . The image sensor of claim 9 , wherein the comparator is configured to operate in a first auto-zero period, a first comparison period, a second auto-zero period, and a second comparison period, and
wherein, in the first comparison period and the second comparison period, the first

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Injun
• Kim Jaehong
• Kim Jinwoo
• Paik Daehwa

Classifications

• H10F39/8037

  the integrated elements comprising a transistor · CPC title

• H04N25/773

  comprising photon counting circuits, e.g. single photon detection [SPD] or single photon avalanche diodes [SPAD] · CPC title

• H04N25/616 Primary

  involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling · CPC title

• H04N25/77 Primary

  Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components · CPC title

• H04N25/709

  Circuitry for control of the power supply · CPC title