Accurate Reduced Gate-Drive Current Limiter

Patent metadata

Field	Value
Publication number	US-2024259014-A1
Application number	US-202418435509-A
Country	US
Kind code	A1
Filing date	Feb 7, 2024
Priority date	Oct 4, 2022
Publication date	Aug 1, 2024
Grant date	—

Abstract

Circuits and methods that limit current through power FETs of power converter to reduce damaging current in-rush events, independent of switching frequency, device mismatches, and PVT variations. Embodiments utilize a closed-loop feedback circuit and/or a calibrated compensation circuit to regulate, substantially independent of frequency, the control voltage VGATE applied to a power FET gate. In a reduced gate-drive mode, connecting a feedback or compensation circuit to the gate of an LDO source-follower FET allows the gate voltage to be regulated to control the LDO output voltage to a final inverter coupled to the gate of a power FET so that VGATE is adjusted to provide a reduced gate-drive to the power FET; connecting to the output of the LDO allows the LDO output voltage to the final inverter to be directly regulated to adjust VGATE; connecting to the gate of the power FET allows VGATE to be directly set.

First claim

What is claimed is:

1 . A gate control circuit for regulating the ON resistance, R ON , of a power FET, including:
(a) a source-follower circuit including a source-follower FET having a conduction channel configured to be coupled to the gate of the power FET and configured to selectively apply at least a first voltage or a second voltage to the gate of the power FET such that the R ON of the power FET in an ON state is lower when the first voltage is applied and higher when the second voltage is applied; and (b) a compensation circuit coupled to one of a gate of the source-follower FET or an output of the source-follower FET and configured to apply a compensation voltage boost to adjust the second voltage to the gate of the power FET to compensate for a gate capacitance of the power FET.

2 . The gate control circuit of claim 1 , wherein the power FET is a component of a power converter, and the gate control circuit applies the compensation voltage boost during a dynamic re-configuration of a conversion ratio of the power converter.

3 . The gate control circuit of claim 1 , wherein the power FET is a component of a power converter, and the gate control circuit applies the compensation voltage boost during a startup period of the power converter.

4 . The gate control circuit of claim 1 , wherein the power FET is a component of a power converter, and the gate control circuit applies the compensation voltage boost during a charge re-balancing event among two or more capacitors within the power converter.

5 . The gate control circuit of claim 1 , wherein the compensation circuit is configured to be coupled between a supply voltage and a reference potential, and includes:
(a) a current source configured to be coupled to the supply voltage; (b) a resistor coupled to the current source and configured to be coupled to the reference potential; and (c) a capacitor coupled to the current source and configured to be coupled to the reference potential, wherein the capacitor is in parallel with the resistor.

6 . The gate control circuit of claim 1 , wherein the source-follower circuit further includes:
(a) a current source coupled between a voltage source and a gate of the source-follower FET; (b) a voltage regulator coupled to the gate of the source-follower FET and configured to provide a voltage; and (c) a voltage control circuit coupled to the gate of the source-follower FET and including a first selectable configuration disconnected from the gate of the source-follower FET, and a second selectable configuration coupled to the gate of the source-follower FET, wherein the voltage at the gate of the source-follower FET when the voltage control circuit is in the first selectable configuration is higher than in the second selectable configuration.

7 . The gate control circuit of claim 6 , wherein the voltage control circuit includes:
(a) a switch; (b) a first diode-connected FET; and (c) at least one additional diode-connected FET;
wherein the switch, the first diode-connected FET, and the at least one additional diode-connected FET are coupled in series between the gate of the source-follower FET and a reference potential.

8 . The gate control circuit of claim 6 , wherein the voltage regulator is a Zener diode.

9 . A gate control circuit for regulating the ON resistance, R ON , of a power FET, including:
(a) a source-follower circuit including a source-follower FET having a conduction channel configured to be selectively coupled to the gate of the power FET and configured to selectively apply a reduced gate-drive voltage to the gate of the power FET such that the R ON of the power FET in an ON state restricts flow of current through the power FET; and (b) a compensation circuit coupled to one of a gate of the source-follower FET or an output of the source-follower FET and configured to apply a compensation voltage boost to adjust the reduced gate-drive voltage to the gate of the power FET to compensate for a gate capacitance of the power FET.

10 . The gate control circuit of claim 9 , wherein the power FET is a component of a power converter, and the gate control circuit applies the compensation voltage boost during a dynamic re-configuration of a conversion ratio of the power converter.

11 . The gate control circuit of claim 9 , wherein the power FET is a component of a power converter, and the gate control circuit applies the compensation voltage boost during a startup period of the power converter.

12 . The gate control circuit of claim 9 , wherein the power FET is a component of a power converter, and the gate control circuit applies the compensation voltage boost during a charge re-balancing event among two or more capacitors within the power converter.

13 . The gate control circuit of claim 9 , wherein the compensation circuit is configured to be coupled between a supply voltage and a reference potential, and includes:
(a) a current source configured to be coupled to the supply voltage; (b) a resistor coupled to the current source and configured to be coupled to the reference potential; and (c) a capacitor coupled to the current source and configured to be coupled to the reference potential, wherein the capacitor is in parallel with the resistor.

14 . The gate control circuit of claim 9 , wherein the source-follower circuit further includes:
(a) a current source coupled between a voltage source and a gate of the source-follower FET; (b) a voltage regulator coupled to the gate of the source-follower FET and configured to provide a voltage; and (c) a voltage control circuit coupled to the gate of the source-follower FET.

15 . The gate control circuit of claim 14 , wherein the voltage control circuit includes:
(a) a first diode-connected FET; and (b) at least one additional diode-connected FET;
wherein the first diode-connected FET and the at least one additional diode-connected FET are coupled in series between the gate of the source-follower FET and a reference potential.

16 . A method of protecting a power converter, including:
(a) controlling the ON resistance, R ON , of a power FET in the power converter to lower the R ON of the power FET in a first ON state during normal power converter operation and to raise the R ON of the power FET in a second ON state to restrict flow of current through the power FET; (b) generating a feedback current proportional to a current flow through the power FET; and (c) regulating the R ON of the power FET in the second ON state in proportion to the generated feedback current to provide a reduced gate-drive voltage to the power FET.

17 . The method of claim 16 , wherein the reduced gate-drive to the power FET is substantially independent of frequency.

18 . The method of claim 16 , further including regulating the R ON of the power FET in the second ON state in proportion to the generated feedback current during a dynamic re-configuration of a conversion ratio of the power converter.

19 . The method of claim 16 , further including regulating the R ON of the power FET in the second ON state in proportion to the generated feedback current during a startup period of the power converter.

20 . The method of claim 16 , further including regulating the R ON of the power FET in the second ON state in proportion to the generated feedback current during a charge re-balancing event among two or more capacitors within the power converter.

Assignees

• Psemi Corp

Inventors

• Vangara Satish Kumar
• Routledge Antony Christopher
• Szczeszynski Gregory
• Sun Xiaowu

Classifications

• H03K5/086 Primary

  generated by feedback · CPC title

• H03K17/0822 Primary

  in field-effect transistor switches · CPC title