Power supply circuit, processing circuit, and wireless communication system

Patent metadata

Field	Value
Publication number	US-2024258972-A1
Application number	US-202218566395-A
Country	US
Kind code	A1
Filing date	Mar 29, 2022
Priority date	Jun 4, 2021
Publication date	Aug 1, 2024
Grant date	—

Abstract

A wireless communication system includes: a processing circuit, at least one linear amplification circuit, a switch amplification circuit, at least one first filter capacitor, and at least one power amplifier. An output end of the switch amplification circuit, an output end of the linear amplification circuit, and a power supply end of the power amplifier are coupled at a first node. The first filter capacitor is coupled to an input end of the linear amplification circuit or the output end of the linear amplification circuit.

First claim

1 - 34 . (canceled)

35 . A system, comprising:
a processing circuit; at least one linear amplification circuit; a switch amplification circuit; at least one first filter capacitor; and at least one power amplifier, wherein an output end of the switch amplification circuit, an output end of the linear amplification circuit, and a power supply end of the power amplifier are coupled at a first node, and the first filter capacitor is coupled to an input end of the linear amplification circuit or to the output end of the linear amplification circuit; wherein the processing circuit is configured to: output a first radio frequency signal, a first envelope signal, and a first drive signal of a first transmit signal, wherein the first drive signal comprises a switch signal of the switch amplification circuit or a second envelope signal, and the switch signal of the switch amplification circuit is generated by the processing circuit based on the second envelope signal; wherein the linear amplification circuit is configured to: receive the first envelope signal, and output a first power supply voltage to the first node; wherein the switch amplification circuit is configured to: receive the first drive signal, and output a second power supply voltage to the first node; and wherein the power amplifier is configured to amplify the first radio frequency signal based on the first power supply voltage and the second power supply voltage.

36 . The system according to claim 35 , wherein
the first envelope signal comprises an envelope signal of a high frequency part in the first transmit signal; or the second envelope signal comprises an envelope signal of a low frequency part and a direct current part in the first transmit signal.

37 . The system according to claim 35 , wherein a highest frequency of the first envelope signal is greater than a highest frequency of the second envelope signal; or
a lowest frequency of the first envelope signal is greater than a lowest frequency of the second envelope signal.

38 . The system according to claim 35 , further comprising a second filter capacitor, wherein the first filter capacitor is coupled to the output end of the linear amplification circuit, and the second filter capacitor is coupled to the input end of the linear amplification circuit.

39 . The system according to claim 35 , further comprising an analog high-pass filter, wherein the first filter capacitor is coupled to the output end of the linear amplification circuit, and the analog high-pass filter is coupled to the input end of the linear amplification circuit.

40 . The system according to claim 35 , wherein the processing circuit is further configured to:
perform shaping filtering on the first transmit signal to generate the first envelope signal; and perform shaping filtering on the first transmit signal to generate the second envelope signal.

41 . The system according to claim 35 , wherein the first filter capacitor is coupled to the output end of the linear amplification circuit, and wherein the processing circuit is further configured to filter out a low frequency part and a direct current part in the first transmit signal to generate the first envelope signal.

42 . The system according to claim 35 , wherein the processing circuit is further configured to:
perform amplitude or phase compensation on the first transmit signal to generate the first envelope signal; or perform amplitude or phase compensation on the first transmit signal to generate the second envelope signal.

43 . The system according to claim 35 , wherein
a length of a trace between the linear amplification circuit and the power amplifier is less than a length of a trace between the switch amplification circuit and the power amplifier.

44 . The system according to claim 35 , wherein the linear amplification circuit and the power amplifier are disposed on a same package substrate.

45 . The system according to claim 35 , wherein the switch amplification circuit comprises a multi-phase or multi-voltage switch amplification circuit.

46 . The system according to claim 35 , wherein:
the at least one linear amplification circuit comprises a first linear amplification circuit and a second linear amplification circuit; the at least one power amplifier comprises a first power amplifier and a second power amplifier; the at least one first filter capacitor comprises a third filter capacitor and a fourth filter capacitor; the output end of the switch amplification circuit, an output end of the first linear amplification circuit, and a power supply end of the first power amplifier are coupled at the first node, and the third filter capacitor is coupled to an input end of the first linear amplification circuit or the output end of the first linear amplification circuit; the output end of the switch amplification circuit, an output end of the second linear amplification circuit, and a power supply end of the second power amplifier are coupled at a second node, and the fourth filter capacitor is coupled to an input end of the second linear amplification circuit or the output end of the second linear amplification circuit; the first linear amplification circuit is configured to receive the first envelope signal and output the first power supply voltage to the first node; and the second linear amplification circuit is configured to receive the first envelope signal and output a third power supply voltage to the second node.

47 . The system according to claim 35 , wherein:
the at least one linear amplification circuit comprises a first linear amplification circuit and a second linear amplification circuit; the at least one power amplifier comprises a first power amplifier and a second power amplifier; the at least one first filter capacitor comprises a third filter capacitor and a fourth filter capacitor; the output end of the switch amplification circuit, an output end of the first linear amplification circuit, and a power supply end of the first power amplifier are coupled at the first node, and the third filter capacitor is coupled to an input end of the first linear amplification circuit or the output end of the first linear amplification circuit; the output end of the switch amplification circuit, an output end of the second linear amplification circuit, and a power supply end of the second power amplifier are coupled at a second node, and the fourth filter capacitor is coupled to an input end of the second linear amplification circuit or the output end of the second linear amplification circuit; and when the first power amplifier is enabled by a first enable signal, the first linear amplification circuit is configured to: receive the first envelope signal and output the first power supply voltage to the first node; or when the second power amplifier is enabled by a second enable signal, the second linear amplification circuit is configured to receive the first envelope signal, and output a third power supply voltage to the second node.

48 . A circuit, comprising:
at least one linear amplification circuit; and a switch amplification circuit, and at least one first filter capacitor, wherein an output end of the linear amplification circuit and an output end of the switch amplification circuit are coupled at a first node, a power supply end of a power amplifier is coupled at the first node, and the first filter capacitor is coupled to an input end of the linear amplification circuit or the output end of the linear amplification circuit; wherein the linear amplification circuit is configured to receive a first envelope signal

Assignees

• Huawei Tech Co Ltd

Inventors

• Wu Jianfeng
• Zhang Yi
• Xue Pan
• Hu Danting
• Chang Hsianghui

Classifications

• H03F3/72

  Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal · CPC title

• H03F2200/432

  Two or more amplifiers of different type are coupled in parallel at the input or output, e.g. a class D and a linear amplifier, a class B and a class A amplifier · CPC title

• H03F3/195

  in integrated circuits · CPC title

• H03F1/0227

  using supply converters · CPC title

• H03F2200/451

  the amplifier being a radio frequency amplifier · CPC title